Switch/Router Architectures

Book description

A practicing engineer's inclusive review of communication systems based on shared-bus and shared-memory switch/router architectures

This book delves into the inner workings of router and switch design in a comprehensive manner that is accessible to a broad audience. It begins by describing the role of switch/routers in a network, then moves on to the functional composition of a switch/router. A comparison of centralized versus distributed design of the architecture is also presented. The author discusses use of bus versus shared-memory for communication within a design, and also covers Quality of Service (QoS) mechanisms and configuration tools.

Written in a simple style and language to allow readers to easily understand and appreciate the material presented, Switch/Router Architectures: Shared-Bus and Shared-Memory Based Systems discusses the design of multilayer switches—starting with the basic concepts and on to the basic architectures. It describes the evolution of multilayer switch designs and highlights the major performance issues affecting each design. It addresses the need to build faster multilayer switches and examines the architectural constraints imposed by the various multilayer switch designs. The book also discusses design issues including performance, implementation complexity, and scalability to higher speeds. This resource also:

  • Summarizes principles of operation and explores the most common installed routers
  • Covers the design of example architectures (shared bus and memory based architectures), starting from early software based designs
  • Provides case studies to enhance reader comprehension

Switch/Router Architectures: Shared-Bus and Shared-Memory Based Systems is an excellent guide for advanced undergraduate and graduate level students, as well for engineers and researchers working in the field.

Table of contents

  1. Cover
  2. Series Page
  3. Title Page
  4. Copyright
  5. About the Author
  6. Preface
  7. Chapter 1: Introduction to Switch/Router Architectures
    1. 1.1 Introducing the Multilayer Switch
    2. 1.2 Evolution of Multilayer Switch Architectures
  8. Chapter 2: Understanding Shared-Bus and Shared-Memory Switch Fabrics
    1. 2.1 Introduction
    2. 2.2 Switch Fabric Design Fundamentals
    3. 2.3 Types of Blocking in Switch Fabrics
    4. 2.4 Emerging Requirements for High-Performance Switch Fabrics
    5. 2.5 Shared Bus Fabric
    6. 2.6 Hierarchical Bus-Based Architecture
    7. 2.7 Distributed Output Buffered Fabric
    8. 2.8 Shared Memory Switch Fabric
    9. 2.9 Shared Ring Fabric
    10. 2.10 Electronic Design Problems
  9. Chapter 3: Shared-Bus and Shared-Memory-Based Switch/Router Architectures
    1. 3.1 Architectures with Bus-Based Switch Fabrics and Centralized Forwarding Engines
    2. 3.2 Architectures with Bus-Based Switch Fabrics and Distributed Forwarding Engines
    3. 3.3 Architectures with Shared-Memory-Based Switch Fabrics and Distributed Forwarding Engines
    4. 3.4 Relating Architectures to Multilayer Switch Types
  10. Chapter 4: Software Requirements for Switch/Routers
    1. 4.1 Introduction
    2. 4.2 Switch/Router Software Development Methods
    3. 4.3 Stability of the Routing Protocols
    4. 4.4 Network Management
    5. 4.5 Switch/Router Performance
    6. 4.6 Interaction Between Layer 3 (Routing) and Layer 2 (Bridging) Functions in Switch/Routers
    7. 4.7 Control and Management of Line Cards
    8. 4.8 Distributed Forwarding
  11. Chapter 5: Architectures with Bus-Based Switch Fabrics: Case Study—Decnis 500/600 Multiprotocol Bridge/Router
    1. 5.1 Introduction
    2. 5.2 In-Place Packet Forwarding in Line Cards
    3. 5.3 Main Architectural Features of the Decnis 500/600
    4. 5.4 Decnic 500/600 Forwarding Philosophy
    5. 5.5 Detail System Architecture
    6. 5.6 Unicast Packet Reception in a Line Card
    7. 5.7 Unicast Packet Transmission in a Line Card
    8. 5.8 Multicast Packet Transmission in a Line Card
  12. Chapter 6: Architectures with Bus-Based Switch Fabrics: Case Study—Fore Systems Powerhub Multilayer Switches
    1. 6.1 Introduction
    2. 6.2 Powerhub 7000 and 6000 Architectures
    3. 6.3 Powerhub Software Architecture
    4. 6.4 Packet Processing in the PowerHub
    5. 6.5 Looking Beyond the First-Generation Architectures
  13. Chapter 7: Architectures with Bus-Based Switch Fabrics: Case Study—Cisco Catalyst 6000 Series Switches
    1. 7.1 Introduction
    2. 7.2 Main Architectural Features of the Catalyst 6000 Series
    3. 7.3 High-Level Architecture of the Catalyst 6000
    4. 7.4 Catalyst 6000 Control Plane Implementation and Forwarding Engines: Supervisor Engines
    5. 7.5 Catalyst 6000 Line Card Architectures
    6. 7.6 Packet Flow in the Catalyst 6000 with Centralized Flow Cache-Based Forwarding
  14. Chapter 8: Architectures with Shared-Memory-Based Switch Fabrics: Case Study—Cisco Catalyst 3550 Series Switches
    1. 8.1 Introduction
    2. 8.2 Main Architectural Features of the Catalyst 3550 Series
    3. 8.3 System Architecture
    4. 8.4 Packet Forwarding
    5. 8.5 Catalyst 3550 Software Features
    6. 8.6 Catalyst 3550 Extended Features
  15. Chapter 9: Architectures with Bus-Based Switch Fabrics: Case Study—Cisco Catalyst 6500 Series Switches with Supervisor Engine 32
    1. 9.1 Introduction
    2. 9.2 Cisco Catalyst 6500 32 Gb/s Shared Switching Bus
    3. 9.3 Supervisor Engine 32
    4. 9.4 Catalyst 6500 Line Cards Supported by Supervisor Engine 32
    5. 9.5 Cisco Catalyst 6500 32 Gb/s Shared Switching Bus Modes
    6. 9.6 Supervisor Engine 32 QoS Features
    7. 9.7 Packet Flow Through Supervisor Engine 32
  16. Chapter 10: Architectures with Shared-Memory-Based Switch Fabrics: Case Study—Cisco Catalyst 8500 CSR Series
    1. 10.1 Introduction
    2. 10.2 Main Architectural Features of the Catalyst 8500 Series
    3. 10.3 The Switch-Route and Route Processors
    4. 10.4 Switch Fabric
    5. 10.5 Line Cards
    6. 10.6 Catalyst 8500 Forwarding Technology and Operations
    7. 10.7 Catalyst 8500 Quality-of-Service Mechanisms
  17. Chapter 11: Quality of Service Mechanisms in the Switch/Routers
    1. 11.1 Introduction
    2. 11.2 QoS Forwarding Operations within a Typical Layer 2 Switch
    3. 11.3 QoS Forwarding Operations within a Typical Multilayer Switch
    4. 11.4 QoS Features in the Catalyst 6500
  18. Chapter 12: Quality of Service Configuration Tools in Switch/Routers
    1. 12.1 Introduction
    2. 12.2 Ingress QoS and Port Trust Settings
    3. 12.3 Ingress and Egress Port Queues
    4. 12.4 Ingress and Egress Queue Thresholds
    5. 12.5 Ingress and Egress QoS Maps
    6. 12.6 Ingress and Egress Traffic Policing
    7. 12.7 Weighted Tail-Drop: Congestion Avoidance with Tail-Drop and Multiple Thresholds
    8. 12.8 Congestion Avoidance with Wred
    9. 12.9 Scheduling with WRR
    10. 12.10 Scheduling with Deficit Weighted Round-Robin (DWRR)
    11. 12.11 Scheduling with Shaped Round-Robin (SRR)
    12. 12.12 Scheduling with Strict Priority Queuing
    13. 12.13 Netflow and Flow Entries
  19. Chapter 13: Case Study: Quality of Service Processing in the Cisco Catalyst 6000 and 6500 Series Switches
    1. 13.1 Introduction
    2. 13.2 Policy Feature Card (PFC)
    3. 13.3 Distributed Forwarding Card (DFC)
    4. 13.4 Port-Based ASICs
    5. 13.5 QoS Mappings
    6. 13.6 QoS Flow in the Catalyst 6000 and 6500 Family
    7. 13.7 Configuring Port Asic-Based QoS on the Catalyst 6000 and 6500 Family
    8. 13.8 IP Precedence and IEEE 802.1p CoS Processing Steps
  20. Appendix A: Ethernet Frame
    1. A.1 Introduction
    2. A.2 Ethernet Frame Format
  21. Appendix B: IPv4 PACKET
    1. B.1 Introduction
    2. B.2 IPv4 Packet Format
    3. B.3 IPv4 ADDRESSING
    4. B.4 Address Resolution
    5. B.5 IPv4 Address Exhaustion
    6. B.6 IPv4 Options
    7. B.7 IPv4 Packet Fragmentation and Reassembly
    8. B.8 IP Packets Encapsulated into Ethernet Frames
    9. B.9 Forwarding IPv4 Packets
  22. References
  23. Index
  24. End User License Agreement

Product information

  • Title: Switch/Router Architectures
  • Author(s): Dr. James Aweya
  • Release date: June 2018
  • Publisher(s): Wiley-IEEE Press
  • ISBN: 9781119486152