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Synchronous Precharge Logic

Synchronous Precharge Logic

by Marek Smoszna
Publisher: Elsevier
Release Date: January 2013
ISBN: 9780123985279
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Book Description

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI.



  • Comprehensive guide to precharge logic
  • Explains both the advantages and disadvantages to help engineers decide when to utilize precharge logic
  • Useful for engineers in a variety of industries

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Dedication
  6. List of figures
  7. List of tables
  8. About the author
  9. 1. Precharge Logic Basics
    1. 1.1 Introduction
    2. 1.2 What Is Precharge Logic?
    3. 1.3 Why Is it Faster than Static Logic?
    4. 1.4 Advantages of Precharge Logic
    5. 1.5 What About Using Other Transistors?
    6. 1.6 Domino Logic
    7. 1.7 Keepers: Improving the Charge Storage
    8. 1.8 Final Comments
  10. 2. Timing
    1. 2.1 Clock Skew Penalty
    2. 2.2 Hold-Time Problem
    3. 2.3 Nonoverlapping Clocks
    4. 2.4 A Better Latch
    5. 2.5 Input Setup Criteria
    6. 2.6 Input Hold Criteria
    7. 2.7 Precharge Timing
    8. 2.8 Skew Tolerant Design
  11. 3. Transistor Sizing
    1. 3.1 Sizing the Pulldown Stack
    2. 3.2 Sizing of the Output Inverter
    3. 3.3 Logical Effort
    4. 3.4 Sizing of the Keeper Device
    5. 3.5 Sizing of the Precharge Device
    6. 3.6 Sizing Precharge Gates with Wires
  12. 4. Noise Tolerance
    1. 4.1 Input-Connected Prechargers
    2. 4.2 Propagated Noise
    3. 4.3 Input Wire Noise
    4. 4.4 Supply-Level Variations
    5. 4.5 Charge Sharing
    6. 4.6 Charge Sharing: Example 1
    7. 4.7 Charge Sharing: Example 2
    8. 4.8 Leakage
    9. 4.9 Clock Coupling on the Internal Dynamic Node
    10. 4.10 Minority Carrier Charge Injection
    11. 4.11 Alpha Particles
    12. 4.12 Noise Induced on Dynamic Nodes Directly
    13. 4.13 Example of Transistor Crosstalk During Precharge
    14. 4.14 CSR Latch Signal Ordering
    15. 4.15 Interfacing to Transmission Gates
  13. 5. Topology Considerations
    1. 5.1 Limitation on Device Stacking
    2. 5.2 Limitation of Logic Width
    3. 5.3 Use of Low/High Vt Transistors
    4. 5.4 Sharing Evaluation Devices
    5. 5.5 Tapering of the Evaluation Device
    6. 5.6 Footed versus Unfooted
    7. 5.7 Compounding Outputs
    8. 5.8 Late Arriving Input on Top
    9. 5.9 Making Keepers Weak
    10. 5.10 Conditional Keepers
    11. 5.11 Placement of the Evaluation Device
  14. 6. Other Precharge Logic Styles
    1. 6.1 MODL
    2. 6.2 NORA Logic
    3. 6.3 Postcharge Logic
    4. 6.4 CD Domino
    5. 6.5 NTP Logic
    6. 6.6 Differential Cascode Voltage Switch Logic
    7. 6.7 DCML
    8. 6.8 SOI Precharge Logic
    9. 6.9 Advanced Work
  15. 7. Clocked Set–Reset Latches
    1. 7.1 Memory Special Cases
    2. 7.2 Building a CSR Latch
    3. 7.3 Time Borrowing
    4. 7.4 Hold-Time Margins
    5. 7.5 Mintime
    6. 7.6 Alternative Topology
    7. 7.7 The Other Phase
    8. 7.8 Two-Input Latch
    9. 7.9 Adding Scan
  16. 8. Layout Considerations
  17. Appendix: Logical Effort
    1. A.1 Derivation of Delay in a Logic Gate
    2. A.2 The Logical Effort of a Single Stage
    3. A.3 Multistage Networks
    4. A.4 Minimum Delay
    5. A.5 Best Number of Stages
  18. References