book

Synchronous Precharge Logic

by Marek Smoszna

January 2013

Intermediate to advanced

112 pages

2h 22m

English

Elsevier

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1.1 Introduction1.2 What Is Precharge Logic?1.3 Why Is it Faster than Static Logic?1.4 Advantages of Precharge Logic1.5 What About Using Other Transistors?1.6 Domino Logic1.7 Keepers: Improving the Charge Storage1.8 Final Comments
2.1 Clock Skew Penalty2.2 Hold-Time Problem2.3 Nonoverlapping Clocks2.4 A Better Latch2.5 Input Setup Criteria2.6 Input Hold Criteria2.7 Precharge Timing2.8 Skew Tolerant Design

3.1 Sizing the Pulldown Stack3.2 Sizing of the Output Inverter3.3 Logical Effort3.4 Sizing of the Keeper Device3.5 Sizing of the Precharge Device3.6 Sizing Precharge Gates with Wires
4.1 Input-Connected Prechargers4.2 Propagated Noise4.3 Input Wire Noise4.4 Supply-Level Variations4.5 Charge Sharing4.6 Charge Sharing: Example 14.7 Charge Sharing: Example 24.8 Leakage4.9 Clock Coupling on the Internal Dynamic Node4.10 Minority Carrier Charge Injection4.11 Alpha Particles4.12 Noise Induced on Dynamic Nodes Directly4.13 Example of Transistor Crosstalk During Precharge4.14 CSR Latch Signal Ordering4.15 Interfacing to Transmission Gates
5.1 Limitation on Device Stacking5.2 Limitation of Logic Width5.3 Use of Low/High Vt Transistors5.4 Sharing Evaluation Devices5.5 Tapering of the Evaluation Device5.6 Footed versus Unfooted5.7 Compounding Outputs5.8 Late Arriving Input on Top5.9 Making Keepers Weak5.10 Conditional Keepers5.11 Placement of the Evaluation Device
6.1 MODL6.2 NORA Logic6.3 Postcharge Logic6.4 CD Domino6.5 NTP Logic6.6 Differential Cascode Voltage Switch Logic6.7 DCML6.8 SOI Precharge Logic6.9 Advanced Work
7.1 Memory Special Cases7.2 Building a CSR Latch7.3 Time Borrowing7.4 Hold-Time Margins7.5 Mintime7.6 Alternative Topology7.7 The Other Phase7.8 Two-Input Latch7.9 Adding Scan
A.1 Derivation of Delay in a Logic GateA.2 The Logical Effort of a Single StageA.3 Multistage NetworksA.4 Minimum DelayA.5 Best Number of Stages

Overview

Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI.

Comprehensive guide to precharge logic
Explains both the advantages and disadvantages to help engineers decide when to utilize precharge logic
Useful for engineers in a variety of industries