Book description
Precharge logic is used by a variety of industries in applications where processor speed is the primary goal, such as VLSI (very large systems integration) applications. Also called dynamic logic, this type of design uses a clock to synchronize instructions in circuits. This comprehensive book covers the challenges faced by designers when using this logic style, including logic basics, timing, noise considerations, alternative topologies and more. In addition advanced topics such as skew tolerant design are covered in some detail. Overall this is a comprehensive view of precharge logic, which should be useful to graduate students and designers in the field alike. It might also be considered as a supplemental title for courses covering VLSI.
- Comprehensive guide to precharge logic
- Explains both the advantages and disadvantages to help engineers decide when to utilize precharge logic
- Useful for engineers in a variety of industries
Table of contents
- Cover image
- Title page
- Table of Contents
- Copyright
- Dedication
- List of figures
- List of tables
- About the author
- 1. Precharge Logic Basics
- 2. Timing
- 3. Transistor Sizing
-
4. Noise Tolerance
- 4.1 Input-Connected Prechargers
- 4.2 Propagated Noise
- 4.3 Input Wire Noise
- 4.4 Supply-Level Variations
- 4.5 Charge Sharing
- 4.6 Charge Sharing: Example 1
- 4.7 Charge Sharing: Example 2
- 4.8 Leakage
- 4.9 Clock Coupling on the Internal Dynamic Node
- 4.10 Minority Carrier Charge Injection
- 4.11 Alpha Particles
- 4.12 Noise Induced on Dynamic Nodes Directly
- 4.13 Example of Transistor Crosstalk During Precharge
- 4.14 CSR Latch Signal Ordering
- 4.15 Interfacing to Transmission Gates
-
5. Topology Considerations
- 5.1 Limitation on Device Stacking
- 5.2 Limitation of Logic Width
- 5.3 Use of Low/High Vt Transistors
- 5.4 Sharing Evaluation Devices
- 5.5 Tapering of the Evaluation Device
- 5.6 Footed versus Unfooted
- 5.7 Compounding Outputs
- 5.8 Late Arriving Input on Top
- 5.9 Making Keepers Weak
- 5.10 Conditional Keepers
- 5.11 Placement of the Evaluation Device
- 6. Other Precharge Logic Styles
- 7. Clocked Set–Reset Latches
- 8. Layout Considerations
- Appendix: Logical Effort
- References
Product information
- Title: Synchronous Precharge Logic
- Author(s):
- Release date: January 2013
- Publisher(s): Elsevier
- ISBN: 9780124017078
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