Synchronous Precharge Logic

4

Noise Tolerance

Precharge logic gates have a much lower noise margin than conventional static CMOS. The noise margin is the amount of noise that can be introduced between a set of logic gates without causing the output gate to switch logic states. Static gates have relatively large noise margins (NM_h=V_oh−V_ih and NM_l=V_il−V_ol). The noise can even exceed the threshold of a transistor without causing the logic gate to switch. In precharge logic, the situation is different. Because the dynamic node is not always driven, any noise that exceeds the threshold of an NMOS device can turn that device on and create a path from the dynamic node to V_ss, discharging the node. The evaluation part of the transfer characteristic transitions at a small input voltage ...