[bib07_0033] [Badereddine 2006] N. Badereddine, P. Girard, S. Pravossoudovitch, C. Landrault, A. Virazel, and H. J. Wunderlich, Minimizing peak power consumption during scan testing: Test pattern modification with X filling heuristics, in Proc. Int. Conf. on Design & Test of Integrated Systems, pp. 259–264, September 2006.

[bib07_0034] [Bonhomme 2001] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, A gated clock scheme for low power scan testing of logic ICs or embedded cores, in Proc. Asian Test Symp., pp. 253–258, November 2001.

[bib07_0035] [Bonhomme 2002] Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch, Power driven chaining of flip-flops in scan architectures, in Proc. Int. Test Conf., pp. 796–803, ...

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