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Terrestrial Radiation Effects in ULSI Devices and Electronic Systems by Eishi H. Ibe

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Chapter 8Mitigation Techniques of Failures in Electronic Components and Systems

8.1 Conventional Stack-layer Based Mitigation Techniques, Their Limitations and Improvements

There are a number of conventional mitigation techniques mainly in device/circuit layers [1, 2]. They are mainly against alpha-ray induced soft error in DRAMs (Dynamic Random Access Memories). As neutron-induced soft error becomes imminent, a number of additional mitigation techniques have been proposed in each stack layer basis. Such layer-based mitigation techniques and their limitations are reviewed in this section.

8.1.1 Substrate/Device Level

Table 8.1 summarises traditional and recent prevention, in-situ recovery and off-line recovery techniques in the substrate/device level [3–21].

Table 8.1 List of prevention, in-situ recovery and off-line mitigation techniques against failures in substrate/device level

Layer Prevention In-situ recovery Off-line recovery
Substrate/well
  1. Confinement of charge collection volume1
  2. Optimisation of well structure/size1
  3. Implementation of fault detectors (BICS2, SAW type detector, on-chip monitor3)
  1. Zone isolation9
  1. Zone isolation13
Device
  1. Addition of resistor and/or capacitor (high-k gate4)
  2. Interleaving of memory cells in the same word5
  3. Gate/transistor sizing6
  4. Addition of guard electrode/contact7
  5. Exchange critical devices to hardened devices8
  1. ECC (SBU only)10
  2. Memory page retirement and re-mapping11
  3. Partial reconfiguration of CRAM12
  1. Power ...

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