Terrestrial Radiation Effects in ULSI Devices and Electronic Systems

Chapter 8Mitigation Techniques of Failures in Electronic Components and Systems

8.1 Conventional Stack-layer Based Mitigation Techniques, Their Limitations and Improvements

There are a number of conventional mitigation techniques mainly in device/circuit layers [1, 2]. They are mainly against alpha-ray induced soft error in DRAMs (Dynamic Random Access Memories). As neutron-induced soft error becomes imminent, a number of additional mitigation techniques have been proposed in each stack layer basis. Such layer-based mitigation techniques and their limitations are reviewed in this section.

8.1.1 Substrate/Device Level

Table 8.1 summarises traditional and recent prevention, in-situ recovery and off-line recovery techniques in the substrate/device level [3–21].

Table 8.1 List of prevention, in-situ recovery and off-line mitigation techniques against failures in substrate/device level

Layer	Prevention	In-situ recovery	Off-line recovery
Substrate/well	Confinement of charge collection volume1 Optimisation of well structure/size1 Implementation of fault detectors (BICS2, SAW type detector, on-chip monitor3)	Zone isolation9	Zone isolation13
Device	Addition of resistor and/or capacitor (high-k gate4) Interleaving of memory cells in the same word5 Gate/transistor sizing6 Addition of guard electrode/contact7 Exchange critical devices to hardened devices8	ECC (SBU only)10 Memory page retirement and re-mapping11 Partial reconfiguration of CRAM12	Power ...