Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

Book Description

Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit.  

  • Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material
  • Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics
  • Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions
  • Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement

Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.

Table of Contents

  1. Cover Page
  2. Title Page
  3. Copy Page
  4. Preface
  5. About the Editors
  6. Contributors
  7. 1 Fundamentals of Small-Delay Defect Testing
    1. 1.1 Introduction
    2. 1.2 Trends and Challenges in Semiconductor Manufacturing
      1. 1.2.1 Process Complexity
      2. 1.2.2 Process Variability
      3. 1.2.3 Random versus Systematic Defects
      4. 1.2.4 Implications of Power and Timing Optimization
      5. 1.2.5 The Interaction of Yield, Quality, and Fault Coverage
    3. 1.3 Existing Test Methods and Challenges of Smaller Geometries
      1. 1.3.1 Line Stuck-at Fault Model
      2. 1.3.2 Bridging Fault Models
      3. 1.3.3 n-Detection
      4. 1.3.4 Transition Fault Model
      5. 1.3.5 Path Delay Fault Model
      6. 1.3.6 Test Implementation and Adaptive Test
    4. 1.4 Effect of Small Delays on Transition Testing
  8. Section I Timing-Aware ATPG
    1. 2 K Longest Paths
      1. 2.1 Introduction
      2. 2.2 Path Generation for Combinational Circuits
        1. 2.2.1 Refined Implicit False Path Elimination
      3. 2.3 Experimental Results for Combinational Circuits
      4. 2.4 Extension to Scan-Based At-Speed Testing of Sequential Circuits
      5. 2.5 Path Generation for Scan Circuits
        1. 2.5.1 Implications on Scanned Flip-Flops
        2. 2.5.2 Constraints from Nonscanned Memories
        3. 2.5.3 Final Justification
      6. 2.6 Experimental Results on Scan Circuits
        1. 2.6.1 Robust Test
        2. 2.6.2 Comparison to Transition Fault Tests
      7. 2.7 Conclusions
    2. 3 Timing-Aware ATPG
      1. 3.1 Introduction
      2. 3.2 Delay Calculation and Quality Metrics
        1. 3.2.1 Delay Calculation
        2. 3.2.2 Delay Test Quality Metrics
          1. 3.2.2.1 Delay Test Coverage
          2. 3.2.2.2 Delay Test Quality Coverage
          3. 3.2.2.3 Statistical Delay Quality Level
      3. 3.3 Deterministic Test Generation
        1. 3.3.1 Test Generation with Timing Data
        2. 3.3.2 Fault Simulation with Timing Data
      4. 3.4 Trade-off between Test Quality and Test Cost
        1. 3.4.1 Dropping Based on Slack Margin
        2. 3.4.2 Timing-Critical Faults
      5. 3.5 Experimental Results
  9. Section II Faster-than-at-Speed
    1. 4 Faster-than-at-Speed Test for Screening Small-Delay Defects
      1. 4.1 Introduction
      2. 4.2 Design Implementation
      3. 4.3 Test Pattern Delay Analysis
        1. 4.3.1 Dynamic IR Drop Analysis at Functional Speed
        2. 4.3.2 Dynamic IR Drop Analysis for the Faster-than-at-Speed Test
      4. 4.4 IR Drop Aware Faster-than-at-Speed Test Technique
        1. 4.4.1 Pattern Grouping
        2. 4.4.2 Estimation of Performance Degradation
      5. 4.5 Experimental Results
      6. 4.6 Conclusions
    2. 5 Circuit Path Grading Considering Layout, Process Variations, and Cross Talk
      1. 5.1 Introduction
        1. 5.1.1 Commercial Methodologies for SDD Detection
        2. 5.1.2 Academic Proposals for SDD Detection
      2. 5.2 Analyzing SDDs Induced by Variations
        1. 5.2.1 Impact of Process Variations on Path Delay
        2. 5.2.2 Impact of Cross Talk on Path Delay
      3. 5.3 TDF Pattern Evaluation and Selection
        1. 5.3.1 Path PDF Analysis
        2. 5.3.2 Pattern Selection
      4. 5.4 Experimental Results and Analysis
        1. 5.4.1 Pattern Selection Efficiency Analysis
        2. 5.4.2 Pattern Set Analysis
        3. 5.4.3 Long-Path Threshold Analysis
        4. 5.4.4 CPU Run Time Analysis
      5. 5.5 Conclusion
  10. Section III Alternative Methods
    1. 6 Output Deviations-Based SDD Testing
      1. 6.1 Introduction
      2. 6.2 The Need for Alternative Methods
      3. 6.3 Probabilistic Delay Fault Model and Output Deviations for SDDs
        1. 6.3.1 Method of Output Deviations
          1. 6.3.1.1 Gate Delay Defect Probabilities
          2. 6.3.1.2 Propagation of Signal Transition Probabilities
          3. 6.3.1.3 Implementation of Algorithm for Propagating Signal Transition Probabilities
          4. 6.3.1.4 Pattern-Selection Method
        2. 6.3.2 Practical Aspects and Adaptation to Industrial Circuits
        3. 6.3.3 Comparison to SSTA-Based Techniques
      4. 6.4 Simulation Results
        1. 6.4.1 Experimental Setup and Benchmarks
        2. 6.4.2 Simulation Results
        3. 6.4.3 Comparison of the Original Method to the Modified Method
      5. 6.5 Conclusions
    2. 7 Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects
      1. 7.1 Introduction
      2. 7.2 Fault Set for Timing-Aware ATPG
      3. 7.3 Small-Delay Defect Pattern Generation
        1. 7.3.1 Approach 1: TDF plus Top-off SDD
        2. 7.3.2 Approach 2: Top-off SDD plus Top-off TDF
      4. 7.4 Experimental Results
      5. 7.5 Conclusion
    3. 8 Circuit Topology-Based Test Pattern Generation for Small-Delay Defects
      1. 8.1 Introduction
      2. 8.2 Circuit Topology-Based Fault Selection
      3. 8.3 SDD Pattern Generation
      4. 8.4 Experimental Results and Analysis
        1. 8.4.1 Delay Test Coverage
        2. 8.4.2 Number of Unique Long Paths
        3. 8.4.3 Length of Longest Path
        4. 8.4.4 Number of Unique SDDs
        5. 8.4.5 Random Fault Injection and Detection
      5. 8.5 Conclusion
  11. Section IV SDD Metrics
    1. 9 Small-Delay Defect Coverage Metrics
      1. 9.1 Role of Coverage Metrics
      2. 9.2 Overview of Existing Metrics
        1. 9.2.1 Delay Test Coverage Metric
          1. 9.2.1.1 Shortcomings of the DTC Metric
        2. 9.2.2 Statistical Delay Quality Level Metric
          1. 9.2.2.1 Shortcomings of the SDQL Metric
      3. 9.3 Proposed SDD Test Coverage Metric
        1. 9.3.1 Quadratic SDD Test Coverage Metric
        2. 9.3.2 Faster-than-at-Speed Testing
      4. 9.4 Experimental Results
        1. 9.4.1 Sensitivity to System Frequency
        2. 9.4.2 Sensitivity to Defect Distribution
        3. 9.4.3 Timing-Aware versus Faster-than-at-Speed
      5. 9.5 Conclusion
    2. 10 Conclusion
  12. Index

Product Information

  • Title: Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits
  • Author(s): Sandeep K. Goel, Krishnendu Chakrabarty
  • Release date: December 2017
  • Publisher(s): CRC Press
  • ISBN: 9781351833707