Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

Preface

Recent years have seen tremendous advances in design methods and process technologies in the semiconductor industry. These advances have resulted in a relentless increase in the complexity of integrated circuits (ICs). Due to high complexity and nanometer feature sizes, today’s ICs are not only susceptible to manufacturing defects such as resistive opens and shorts, but also affected by process variations, power-supply noise, cross talk, and rule violations related to design for manufacturability (DfM), such as butted contacts and insufficient via enclosures. These defects and abnormalities introduce small delays in the circuit, collectively referred to as small-delay defects (SDDs). Concern about SDDs in the semiconductor industry is ...