Chapter 7. Memory System

Overview

In this chapter we will look into the memory architecture of the Cortex-M0 processor and how it affects software development.
The Cortex-M0 processor has a 32-bit system bus interface with 32-bit address lines (4 GB of address space). The system bus is based on a bus protocol called AHB-Lite (Advanced High-performance Bus), which is a protocol defined in the Advanced Microcontroller Bus Architecture (AMBA) standard. The AMBA standard is developed by ARM, and is widely used in the semiconductor industry.
Although the AHB-Lite protocol provides high-performance accesses to the memory system, very often a secondary bus segment can also be found for slower devices including peripherals. In ARM microcontrollers, the peripheral ...

Get The Definitive Guide to the ARM Cortex-M0 now with O’Reilly online learning.

O’Reilly members experience live online training, plus books, videos, and digital content from 200+ publishers.