The Definitive Guide to the ARM Cortex-M3, 2nd Edition

The Definitive Guide to the ARM Cortex-M3, 2nd Edition

by Joseph Yiu
Released November 2009
Publisher(s): Newnes
ISBN: 9781856179645

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Book description

This user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap!

Whole chapters are dedicated to:
Debugging using the new CoreSight technology
Migrating effectively from the ARM7
The Memory Protection Unit
Interfaces, Exceptions,Interrupts
...and much more!
  • The only available guide to programming and using the groundbreaking ARM Cortex-M3 processor
  • Easy-to-understand examples, diagrams, quick reference appendices, full instruction and Thumb-2 instruction sets are included 
  • T teaches end users how to start from the ground up with the M3, and how to migrate from the ARM7

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Foreword
  6. Foreword
  7. Preface
    1. Acknowledgments
  8. Conventions
  9. Terms and Abbreviations
  10. CHAPTER 1. Introduction
    1. Publisher Summary
    2. 1.1 What Is the ARM Cortex-M3 Processor?
    3. 1.2 Background of ARM and ARM Architecture
    4. 1.3 Instruction Set Development
    5. 1.4 The Thumb-2 Technology and Instruction Set Architecture
    6. 1.5 Cortex-M3 Processor Applications
    7. 1.6 Organization of This Book
    8. 1.7 Further Reading
  11. CHAPTER 2. Overview of the Cortex-M3
    1. Publisher Summary
    2. 2.1 Fundamentals
    3. 2.2 Registers
    4. 2.3 Operation Modes
    5. 2.4 The Built-In Nested Vectored Interrupt Controller
    6. 2.5 The Memory Map
    7. 2.6 The Bus Interface
    8. 2.7 The MPU
    9. 2.8 The Instruction Set
    10. 2.9 Interrupts and Exceptions
    11. 2.10 Debugging Support
    12. 2.11 Characteristics Summary
  12. CHAPTER 3. Cortex-M3 Basics
    1. Publisher Summary
    2. 3.1 Registers
    3. 3.2 Special Registers
    4. 3.3 Operation Mode
    5. 3.4 Exceptions and Interrupts
    6. 3.5 Vector Tables
    7. 3.6 Stack Memory Operations
    8. 3.7 Reset Sequence
  13. CHAPTER 4. Instruction Sets
    1. Publisher Summary
    2. 4.1 Assembly Basics
    3. 4.2 Instruction List
    4. 4.3 Instruction Descriptions
    5. 4.4 Several Useful Instructions In the Cortex-M3
  14. CHAPTER 5. Memory Systems
    1. Publisher Summary
    2. 5.1 Memory System Features Overview
    3. 5.2 Memory Maps
    4. 5.3 Memory Access Attributes
    5. 5.4 Default Memory Access Permissions
    6. 5.5 Bit-Band Operations
    7. 5.6 Unaligned Transfers
    8. 5.7 Exclusive Accesses
    9. 5.8 Endian Mode
  15. CHAPTER 6. Cortex-M3 Implementation Overview
    1. Publisher Summary
    2. 6.1 The Pipeline
    3. 6.2 A Detailed Block Diagram
    4. 6.3 Bus Interfaces on the Cortex-M3
    5. 6.4 Other Interfaces on the Cortex-M3
    6. 6.5 The External PPB
    7. 6.6 Typical Connections
    8. 6.7 Reset Types and Reset Signals
  16. CHAPTER 7. Exceptions
    1. Publisher Summary
    2. 7.1 Exception Types
    3. 7.2 Definitions of Priority
    4. 7.3 Vector Tables
    5. 7.4 Interrupt Inputs and Pending Behavior
    6. 7.5 Fault Exceptions
    7. 7.6 Supervisor Call and Pendable Service Call
  17. CHAPTER 8. The Nested Vectored Interrupt Controller and Interrupt Control
    1. Publisher Summary
    2. 8.1 Nested Vectored Interrupt Controller Overview
    3. 8.2 The Basic Interrupt Configuration
    4. 8.3 Example Procedures In Setting Up an Interrupt
    5. 8.4 Software Interrupts
    6. 8.5 The SYSTICK Timer
  18. CHAPTER 9. Interrupt Behavior
    1. Publisher Summary
    2. 9.1 Interrupt/Exception Sequences
    3. 9.2 Exception Exits
    4. 9.3 Nested Interrupts
    5. 9.4 Tail-Chaining Interrupts
    6. 9.5 Late Arrivals
    7. 9.6 More on the Exception Return Value
    8. 9.7 Interrupt Latency
    9. 9.8 Faults Related to Interrupts
  19. CHAPTER 10. Cortex-M3 Programming
    1. Publisher Summary
    2. 10.1 Overview
    3. 10.2 A Typical Development Flow
    4. 10.3 Using C
    5. 10.4 CMSIS
    6. 10.5 Using Assembly
    7. 10.6 Using Exclusive Access for Semaphores
    8. 10.7 Using Bit Band for Semaphores
    9. 10.8 Working with Bit Field Extract and Table Branch
  20. CHAPTER 11. Exception Programming
    1. Publisher Summary
    2. 11.1 Using Interrupts
    3. 11.2 Exception/Interrupt Handlers
    4. 11.3 Software Interrupts
    5. 11.4 Example of Vector Table Relocation
    6. 11.5 Using SVC
    7. 11.6 SVC Example: Use for Text Message Output Functions
    8. 11.7 Using SVC with C
  21. CHAPTER 12. Advanced Programming Features and System Behavior
    1. Publisher Summary
    2. 12.1 Running a System with Two Separate Stacks
    3. 12.2 Double-Word Stack Alignment
    4. 12.3 Nonbase Thread Enable
    5. 12.4 Performance Considerations
    6. 12.5 Lockup Situations
    7. 12.6 FAULTMASK
  22. CHAPTER 13. The Memory Protection Unit
    1. Publisher Summary
    2. 13.1 Overview
    3. 13.2 MPU Registers
    4. 13.3 Setting Up the MPU
    5. 13.4 Typical Setup
  23. CHAPTER 14. Other Cortex-M3 Features
    1. Publisher Summary
    2. 14.1 The Systick Timer
    3. 14.2 Power Management
    4. 14.3 Multiprocessor Communication
    5. 14.4 Self-Reset Control
  24. CHAPTER 15. Debug Architecture
    1. Publisher Summary
    2. 15.1 Debugging Features Overview
    3. 15.2 Coresight Overview
    4. 15.3 Debug Modes
    5. 15.4 Debugging Events
    6. 15.5 Breakpoint in the Cortex-M3
    7. 15.6 Accessing Register Content in Debug
    8. 15.7 Other Core Debugging Features
  25. CHAPTER 16. Debugging Components
    1. Publisher Summary
    2. 16.1 Introduction
    3. 16.2 Trace Components: DWT
    4. 16.3 Trace Components: ITM
    5. 16.4 Trace Components: ETM
    6. 16.5 Trace Components: TPIU
    7. 16.6 The Flash Patch and Breakpoint Unit
    8. 16.7 The Advanced High-Performance Bus Access Port
    9. 16.8 ROM Table
  26. CHAPTER 17. Getting Started with the Cortex-M3 Processor
    1. Publisher Summary
    2. 17.1 Choosing a Cortex-M3 Product
    3. 17.2 Development Tools
    4. 17.3 Differences between the Cortex-M3 Revision 0 and Revision 1
    5. 17.4 Differences between the Cortex-M3 Revision 1 and Revision 2
    6. 17.5 Benefits and Effects of the Revision 2 New Features
    7. 17.6 Differences between the Cortex-M3 and Cortex-M0
  27. CHAPTER 18. Porting Applications from the ARM7 to the Cortex-M3
    1. Publisher Summary
    2. 18.1 Overview
    3. 18.2 System Characteristics
    4. 18.3 Assembly Language Files
    5. 18.4 C Program Files
    6. 18.5 Precompiled Object Files
    7. 18.6 Optimization
  28. CHAPTER 19. Starting Cortex-M3 Development Using the GNU Tool Chain
    1. Publisher Summary
    2. 19.1 Background
    3. 19.2 Getting the GNU Tool Chain
    4. 19.3 Development Flow
    5. 19.4 Examples
    6. 19.5 Accessing Special Registers
    7. 19.6 Using Unsupported Instructions
    8. 19.7 Inline Assembler in the GNU C Compiler
  29. CHAPTER 20. Getting Started with the Keil RealView Microcontroller Development Kit
    1. Publisher Summary
    2. 20.1 Overview
    3. 20.2 Getting Started with μVision
    4. 20.3 Outputting the “Hello World” Message Via Universal Asynchronous Receiver/Transmitter
    5. 20.4 Testing the Software
    6. 20.5 Using the Debugger
    7. 20.6 The Instruction Set Simulator
    8. 20.7 Modifying the Vector Table
    9. 20.8 Stopwatch Example with Interrupts with CMSIS
    10. 20.9 Porting Existing Applications to Use CMSIS
  30. CHAPTER 21. Programming the Cortex-M3 Microcontrollers in NI LabVIEW
    1. Publisher Summary
    2. 21.1 Overview
    3. 21.2 What Is LabVIEW
    4. 21.3 Development Flow
    5. 21.4 Example of a LabVIEW Project
    6. 21.5 How It Works
    7. 21.6 Additional Features in LabVIEW
    8. 21.7 Porting to Another ARM Processor
  31. APPENDIX A. The Cortex-M3 Instruction Set, Reference Material
    1. A.1 Instruction Set Summary
    2. A.2 About the Instruction Descriptions
    3. A.3 Memory Access Instructions
    4. A.4 General Data-Processing Instructions
    5. A.5 Multiply and Divide Instructions
    6. A.6 Saturating Instructions
    7. A.7 Bitfield Instructions
    8. A.8 Branch and Control Instructions
    9. A.9 Miscellaneous Instructions
  32. APPENDIX B. The 16-Bit Thumb Instructions and Architecture Versions
  33. APPENDIX C. Cortex-M3 Exceptions Quick Reference
    1. C.1 Exception Types and Enables
    2. C.2 Stack Contents After Exception Stacking
  34. APPENDIX D. Nested Vectored Interrupt Controller and System Control Block Registers Quick Reference
  35. APPENDIX E. Cortex-M3 Troubleshooting Guide
    1. E.1 Overview
    2. E.2 Developing Fault Handlers
    3. E.3 Understanding the Cause of the Fault
    4. E.4 Other Possible Problems
  36. APPENDIX F. Example Linker Script for CodeSourcery G++
    1. F.1 Example Linker Script for Cortex-M3
  37. APPENDIX G. CMSIS Core Access Functions Reference
    1. G.1 Exception and Interrupt Numbers
    2. G.2 NVIC Access Functions
    3. G.3 System and SysTick Functions
    4. G.4 Core Registers Access Functions
    5. G.5 CMSIS Intrinsic Functions
    6. G.6 Debug Message Output Function
  38. APPENDIX H. Connectors for Debug and Tracers
    1. H.1 Overview
    2. H.2 The 20-Pin Cortex Debug + ETM Connector
    3. H.3 The 10-Pin Cortex Debug Connector
    4. H.4 Legacy 20-Pin IDC Connector
    5. H.5 Legacy 38-Pin Mictor Connector
  39. References
  40. Index

Product information

  • Title: The Definitive Guide to the ARM Cortex-M3, 2nd Edition
  • Author(s): Joseph Yiu
  • Release date: November 2009
  • Publisher(s): Newnes
  • ISBN: 9781856179645