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The Designer's Guide to the Cortex-M Processor Family

Book Description

The Designer’s Guide to the Cortex-M Family is a tutorial-based book giving the key concepts required to develop programs in C with a Cortex M- based processor. The book begins with an overview of the Cortex- M family, giving architectural descriptions supported with practical examples, enabling the engineer to easily develop basic C programs to run on the Cortex- M0/M0+/M3 and M4. It then examines the more advanced features of the Cortex architecture such as memory protection, operating modes and dual stack operation. Once a firm grounding in the Cortex M processor has been established the book introduces the use of a small footprint RTOS and the CMSIS DSP library.

With this book you will learn:

  • The key differences between the Cortex M0/M0+/M3 and M4
  • How to write C programs to run on Cortex-M based processors
  • How to make best use of the Coresight debug system
  • How to do RTOS development
  • The Cortex-M operating modes and memory protection
  • Advanced software techniques that can be used on Cortex-M microcontrollers
  • How to optimise DSP code for the cortex M4 and how to build real time DSP systems
  • An Introduction to the Cortex microcontroller software interface standard (CMSIS), a common framework for all Cortex M- based microcontrollers
  • Coverage of the CMSIS DSP library for Cortex M3 and M4
  • An evaluation tool chain IDE and debugger which allows the accompanying example projects to be run in simulation on the PC or on low cost hardware

Table of Contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Dedication
  5. Copyright
  6. Foreword
  7. Preface
  8. Acknowledgments
  9. About the Author
  10. Chapter 1. Introduction to the Cortex-M Processor Family
    1. Cortex Profiles
    2. Cortex-M3
    3. Advanced Architectural Features
    4. Cortex-M0
    5. Cortex-M0+
    6. Cortex-M4
    7. DSP Instructions
  11. Chapter 2. Developing Software for the Cortex-M Family
    1. Introduction
    2. Keil Microcontroller Development Kit
    3. The Tutorial Exercises
    4. Installation
    5. Exercise Building a First Program
    6. The Blinky Project
    7. Project Configuration
    8. Hardware Debug
  12. Chapter 3. Cortex-M Architecture
    1. Introduction
    2. Cortex-M Instruction Set
    3. Programmer’s Model and CPU Registers
    4. Program Status Register
    5. Q Bit and Saturated Math Instructions
    6. Interrupts and Multicycle Instructions
    7. Conditional Execution—IF THEN Blocks
    8. Exercise: Saturated Math and Conditional Execution
    9. Cortex-M Memory Map and Busses
    10. Write Buffer
    11. Memory Barrier Instructions
    12. System Control Block
    13. Bit Manipulation
    14. Exercise: Bit Banding
    15. Dedicated Bit Manipulation Instructions
    16. Systick Timer
    17. Nested Vector Interrupt Controller
    18. Operating Modes
    19. Interrupt Handling—Entry
    20. Interrupt Handling—Exit
    21. Interrupt Handling—Exit: Important!
    22. Exercise: Systick Interrupt
    23. Cortex-M Processor Exceptions
    24. Priority and Preemption
    25. Groups and Subgroups
    26. Run Time Priority Control
    27. Exception Model
    28. Exercise: Working with Multiple Interrupts
    29. Bootloader Support
    30. Exercise: Bootloader
    31. Power Management
    32. Moving from the Cortex-M3
    33. Cortex-M4
    34. Cortex-M0
    35. Cortex-M0+
  13. Chapter 4. Cortex Microcontroller Software Interface Standard
    1. Introduction
    2. CMSIS Specifications
    3. CMSIS Core
    5. CMSIS DSP
    6. CMSIS SVD and DAP
    7. Foundations of CMSIS
    8. Coding Rules
    9. MISRA C
    10. CMSIS Core Structure
    11. Startup Code
    12. System Code
    13. Device Header File
    14. CMSIS Core Header Files
    15. Interrupts and Exceptions
    16. Exercise: CMSIS and User Code Comparison
    17. CMSIS Core Register Access
    18. CMSIS Core CPU Intrinsic Instructions
    19. Exercise: Intrinsic Bit Manipulation
    20. CMSIS SIMD Intrinsics
    21. CMSIS Core Debug Functions
    22. Exercise: Simple ITM
  14. Chapter 5. Advanced Architecture Features
    1. Introduction
    2. Cortex Processor Operating Modes
    3. Exercise: Stack Configuration
    4. Supervisor Call
    5. Exercise: SVC
    6. Pend_SVC Exception
    7. Example: Pend_SVC
    8. Interprocessor Events
    9. Exclusive Access
    10. Exercise: Exclusive Access
    11. Memory Protection Unit
    12. Configuring the MPU
    13. Exercise: MPU Configuration
    14. MPU Subregions
    15. MPU Limitations
    16. AHB Lite Bus Interface
  15. Chapter 6. Developing with CMSIS RTOS
    1. Introduction
    2. Getting Started
    3. Setting Up a Project
    4. First Steps with CMSIS RTOS
    5. Threads
    6. Starting the RTOS
    7. Exercise: A First CMSIS RTOS Project
    8. Creating Threads
    9. Exercise: Creating and Managing Threads
    10. Thread Management and Priority
    11. Exercise: Creating and Managing Threads II
    12. Multiple Instances
    13. Exercise: Multiple Thread Instances
    14. Build the Code and Start the Debugger
    15. Time Management
    16. Time Delay
    17. Waiting for an Event
    18. Exercise: Time Management
    19. Virtual Timers
    20. Exercise: Virtual Timer
    21. Idle Demon
    22. Exercise Idle Thread
    23. Interthread Communication
    24. Exercise: Signals
    25. Exercise: Interrupt Signal
    26. Exercise: CMSIS RTX and SVC Exceptions
    27. Exercise: Semaphore Signaling
    28. Exercise: Rendezvous
    29. Exercise: Semaphore Barrier
    30. Message Queue
    31. Exercise: Message Queue
    32. Memory Pool
    33. Mail Queue
    34. Exercise: Mailbox
  16. Chapter 7. Practical DSP for the Cortex-M4
    1. Introduction
    2. Cortex-M4 Hardware Floating Point Unit
    3. FPU Integration
    4. FPU Registers
    5. Enabling the FPU
    6. Exceptions and the FPU
    7. Using the FPU
    8. Exercise: Floating Point Unit
    9. Cortex-M4 DSP and SIMD Instructions
    10. Exercise: SIMD Instructions
    11. Exercise: Optimizing DSP Algorithms
    12. The CMSIS DSP Library
    13. CMSIS DSP Library Functions
    14. Exercise: Using the Library
    15. DSP Data Processing Techniques
    16. Exercise: FIR Filter with Block Processing
    17. Fixed Point DSP with Q Numbers
    18. Exercise: Fixed Point FFT
    19. Designing for Real-Time Processing
    20. Buffering Techniques: The Double or Circular Buffer
    21. Buffering Techniques: FIFO Message Queue
    22. Balancing the Load
    23. Exercise: RTX IIR
    24. Shouldering the Load, the Direct Memory Access Controller
  17. Chapter 8. Debugging with CoreSight
    1. Introduction
    2. CoreSight Hardware
    3. Debugger Hardware
    4. CoreSight Debug Architecture
    5. Exercise: CoreSight Debug
    6. Hardware Configuration
    7. Software Configuration
    8. Debug Limitations
    9. Instrumentation Trace
    10. Exercise: Setting Up the ITM
    11. Software Testing Using the ITM with RTX RTOS
    12. Error Task
    13. Software Test Task
    14. Exercise: Software Testing with the ITM
    15. Instruction Trace with the ETM
    16. Exercise: Using the ETM Trace
    17. System Control Block Debug Support
    18. Tracking Faults
    19. Exercise: Processor Fault Exceptions
    20. CMSIS SVD
    21. Exercise: CMSIS SVD
    22. CMSIS DAP
    23. Cortex-M0+ MTB
    24. Exercise: MTB
    25. Debug Features Summary
  18. Appendix
    1. Debug Tools and Software
    2. Books
    3. Silicon Vendors
    4. Accreditation
    5. Contact Details
  19. Index