Fault Tolerance in Computer Systems—From Circuits to Algorithms*
Shantanu Dutt*, Federico Rota*,†;, Franco Trovo*,†; and Fran Hanchek‡, *Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago, Illinois, USA; †Politecnico di Torina, Italy; ‡Intel Corporation, Portland, Oregon, USA
8.1. Introduction
8.1.1. Dependability and Fault-Tolerance Definitions
8.1.2. Some Basics of Error Detection and Fault Tolerance
8.1.3. Fault Models
8.2. Fault Detection and Tolerance for Arithmetic Circuits
8.2.1. The Reprocessing with Micro Delays Method
8.3. Fault Tolerance in Field-Programmable Gate Arrays
8.3.1. The Static Node-Covering Approach
8.3.2. The Dynamic Node-Covering Approach
8.4. Control Flow ...
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