The ESD Handbook

11ESD Architecture and Floor Planning

11.1 ESD Design Floor Plan

One of the most fundamental issues and challenges in the electrostatic discharge (ESD) design discipline is ESD architecture and floor planning [1–125]. The integration of the devices, circuits, sub-functions and cores is critical to the success of electrical overstress (EOS) and ESD robust designs. In each application space, the floor plan and layout of a semiconductor chip may be different, leading to unique challenges for ESD protection design. Whether it is dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile read access memory (NVRAM), microprocessor, control processor unit (CPU), application specific integrated circuit (ASICs), or semiconductor foundry, each has unique challenges for ESD design. Whether it is single voltage, mixed voltage or mixed signal (MS), the ESD design strategy and architecture has to be modified. Additionally, complementary metal-oxide semiconductor (CMOS), bipolar and complementary metal-oxide semiconductor (BiCMOS), and bipolar-complementary metal-oxide semiconductor-double-diffused metal-oxide-semiconductor (BCD) technology produce digital, analog, power and radio frequency (RF) applications with integration, layout, and design.

In this chapter, one of the goals is to teach how to construct a semiconductor chip to achieve an ESD robust implementation. A significant focus in publications addresses semiconductor device physics and ESD circuits, but ...