The ESD Handbook

16ESD in Advanced CMOS

16.1 Interconnects and ESD

This chapter will focus on CMOS technology and scaling [1–31]. In this chapter, interconnects and their importance in electrostatic discharge (ESD) robustness in semiconductor components will be discussed [26–27]. The chapter will discuss the evolution of interconnects from aluminum-based interconnects, to copper interconnects, and copper/low-k inter-level dielectric (ILD) interconnect systems. These models will be extended to address voids, and insulator “fill shapes.” The chapter will also discuss the role of micro-structure changes and material changes as a result of ESD events. A brief discussion will include the issue of insulator thermal and mechanical stress effects from ESD events. Although there are a number of interconnect models, the focus will be on a few of these models. Hence, the models of Wunsch–Bell, Tasca and Smith-Littau are all appropriate to addressing interconnects. The distinction is the boundary conditions and geometric distinctions of modern interconnect systems. Instead of repeating an exhaustive list of interconnect models, new issues such as Ti/Al/Ti, Cu, low-k dielectrics, fill shapes, voiding, ESD – electromigration studies, and other issues are briefly addressed. These models are also suitable and applicable for understanding ESD failures in magnetic recording devices such as Magneto-resistive heads, Giant Magneto-resistive heads, and Tunneling Magneto-resistive heads.

High current robustness of ...