
Software and Drivers 435
Table 10.2 PCI Header
DWs Offset byte n+3 byte n+2 byte n+1 byte n
0 0000h
Identifi ers (ID)
Device ID Vendor ID
1 0004h Status Register (STS) Command Register (CMD)
2 0008h
Class Codes (CC)
Revision ID
Base Class Code
(BCC)
Sub Class Code
(SCC)
Programming
Interface (PI)
3 000Ch Built-in Self Test
(BIST)
Header Type
(HTYPE = 0)
Master Latency
Timer (MTL)
Cache Line
Sequence (CLS)
4 0010h BAR0
5 0014h BAR1
6 0018h BAR2
7 001Ch BAR3
8 0020h BAR4
9 0024h ABAR (BAR5) AHCI Base Address
10 0028h CardBus CIS Pointer (CCPTR)
11 002Ch Subsystem Identifi ers (SS)
12 0030h Expansion ROM Base Address (Optional) (EROM)
13 0034h Reserved (R) ...