
146 The Essential Guide to Serial ATA and SATA Express
DRQ – will be set to one.
CHK – will be cleared to zero.
Bus release (overlap feature set only)
After receiving the command packet, the device sets BSY to one and clears DRQ to zero. If the com-
mand packet requires a data transfer, the OVL bit is set to one, the Release interrupt is disabled, and
the device is not prepared to immediately transfer data, the device may perform a bus release by placing
the following register content in the Command Block registers. If the command packet requires a data
transfer, the OVL bit is set to one, and the Release interrupt is enabled, the device will pe ...