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The Essential Guide to Serial ATA and SATA Express
book

The Essential Guide to Serial ATA and SATA Express

by David A. Deming
October 2014
Intermediate to advanced content levelIntermediate to advanced
496 pages
15h 38m
English
Auerbach Publications
Content preview from The Essential Guide to Serial ATA and SATA Express
146 The Essential Guide to Serial ATA and SATA Express
DRQ – will be set to one.
CHK – will be cleared to zero.
Bus release (overlap feature set only)
After receiving the command packet, the device sets BSY to one and clears DRQ to zero. If the com-
mand packet requires a data transfer, the OVL bit is set to one, the Release interrupt is disabled, and
the device is not prepared to immediately transfer data, the device may perform a bus release by placing
the following register content in the Command Block registers. If the command packet requires a data
transfer, the OVL bit is set to one, and the Release interrupt is enabled, the device will pe ...
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Publisher Resources

ISBN: 9781482243314