
228 The Essential Guide to Serial ATA and SATA Express
3. Data FIS
1. DD Programs HA DMA
Controller:
x sets pointers
x sets direction
2. DD writes to Shadow
Block Registers
x BSY = 1
4. HA recognizes incoming
Data FIS.
x Directs incoming data
to DMA Controller
Host detects Interrupt
x Checks Status
x BSY = 0
2. Register – Host to Device FIS
Read DMA Command
3. Device Processes
Command
x Prepares Data
x Transmits Data in
one or more Data
FISs
5. Device sends Status
Data FIS
5. Register – Device to Host FIS
Status
3. When the device has processed the command and is ready, it transmits the read data to the host
in the ...