SATA Transport Layer 233
4.2.8 WRITE DMA QUEUED Example
Note: Serial implementations of ATA devices may choose to not implement the parallel implementation
of ATA queuing in favor of a more efficient serial implementation queuing mechanism.
1. Prior to the command being issued to the device, the host driver software programs the host-side
DMA controller with the memory address pointer(s) and the transfer direction, and arms the
DMA controller (enables the “run” flag).
2. The host driver software issues the command to the device by writing the Shadow Command
Block and Shadow Control Block (Command register last).
In response to the Shadow Command Register being written, the host adapter sets the BSY
bit in the Shadow Status register ...