
238 The Essential Guide to Serial ATA and SATA Express
7. When the device has processed the command and is ready, it transmits the read data to the host
in the form of a single Data FIS.
This transfer proceeds in response to flow control signals/readiness.
8. The host adapter recognizes that the incoming packet is a Data FIS and the DMA controller is
programmed, and directs the incoming data to the host adapter’s DMA controller, which for-
wards the incoming data to the appropriate host memory locations.
9. Upon completion of the transfer, the target transmits a Register – Device to Host FIS to indicate
command completion status, ...