The System Designer's Guide to VHDL-AMS

appendix E

VHDL-AMS Syntax

In this appendix we present the full set of syntax rules for VHDL-AMS using the EBNF notation introduced in Chapter 1. The form of EBNF used in this book differs from that of the VHDL-AMS standard in order to make the syntax rules more intelligible to the VHDL user. The standard includes a separate syntax rule for each minor syntactic category. In this book, we condense the grammar into a smaller number of rules, each of which defines a larger part of the grammar. We introduce the EBNF symbols “”, “” and “” as part of ...