Please note the following:
The Time Stamp Counter (TSC) register was introduced in the Pentium® and is present in all subsequent IA32 processors. All of the other MSRs shown in the table were introduced in the Pentium® Pro.
Although the Pentium® Pro does not implement the Pentium®-specific P5_MC_ADDR and P5_MC_TYPE registers [see “Machine Check Architecture (MCA)” on page 504], accesses attempted to these registers will not cause an exception.
The Pentium® Pro does not implement the Pentium®-specific CESR (Performance Counter Event Select Register), or the CTR0 and CTR1 registers and access attempts to these registers will cause an exception.