O'Reilly logo

The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

The Pentium® II and Pentium® III MSRs

Table 28-1 on page 696 defines the MSRs implemented in the Pentium® II and the Pentium® III processors. The newly added registers are the ones in the BBL (Backside Bus Logic) and the Fast System Enter/Exit register groups (all of the others were present in the Pentium® Pro).

Table 28-1. Pentium® II and III MSRs
Reg Address (specified in ECX before executing RDMSR or WRMSR)Register NameDescription
HexDecimal
Miscellaneous MSRs
000h0P5_MC_ADDRPlease note that, although these are Pentium®-specific MSRs, they can be accessed in all post-Pentium® processors without causing an exception.
001h1P5_MC_TYPE
010h16TSCThe Time Stamp Counter (TSC) register was introduced in the Pentium® and is present in all subsequent IA32 ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required