The Pentium® II and Pentium® III MSRs
Table 28-1 on page 696 defines the MSRs implemented in the Pentium® II and the Pentium® III processors. The newly added registers are the ones in the BBL (Backside Bus Logic) and the Fast System Enter/Exit register groups (all of the others were present in the Pentium® Pro).
|Reg Address (specified in ECX before executing RDMSR or WRMSR)||Register Name||Description|
|000h||0||P5_MC_ADDR||Please note that, although these are Pentium®-specific MSRs, they can be accessed in all post-Pentium® processors without causing an exception.|
|010h||16||TSC||The Time Stamp Counter (TSC) register was introduced in the Pentium® and is present in all subsequent IA32 ...|