The Pentium® II and Pentium® III MSRs

Table 28-1 on page 696 defines the MSRs implemented in the Pentium® II and the Pentium® III processors. The newly added registers are the ones in the BBL (Backside Bus Logic) and the Fast System Enter/Exit register groups (all of the others were present in the Pentium® Pro).

Table 28-1. Pentium® II and III MSRs
Reg Address (specified in ECX before executing RDMSR or WRMSR)Register NameDescription
Miscellaneous MSRs
000h0P5_MC_ADDRPlease note that, although these are Pentium®-specific MSRs, they can be accessed in all post-Pentium® processors without causing an exception.
010h16TSCThe Time Stamp Counter (TSC) register was introduced in the Pentium® and is present in all subsequent IA32 ...

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