The Unabridged Pentium 4 IA32 Processor Genealogy

The Big Picture

Although the entire machine (i.e., processor) is pipelined, this chapter conceptually segments the discussion into the front-end pipeline stages and the μop pipeline stages (Intel®'s public domain documentation commonly refers to the μop pipeline stages as the instruction pipeline stages). The reader should not confuse the IA32 instructions with the equivalent μops into which they are decoded.

The processor's core logic is pictured in the following illustrations:

• Figure 38-2 on page 901 pictures the front-end pipeline stages. These are the stages that fetch legacy IA32 instructions from memory, decode the instructions into μops, caches the μops in the Trace Cache, queues them up, and feeds them to the μop pipeline (pictured in ...