The Unabridged Pentium 4 IA32 Processor Genealogy

Chapter 40. The Pentium^® 4 Caches

The Previous Chapter

This chapter provided a detailed description of Hyper-Threading and included:

• Multithreading Overview.

• How Threads Are Assigned in an SMP System.

• CMP Is Another Solution.

• Traditional Single-Processor Multithreading.

• Detecting HT Capability.

• Enabling/Disabling HT.

• Each Logical Processor Has Its Own Local APIC.

• HT Processor Resource Types.

• The HT States.

• Processor Enumeration.

• OS Support for HT.

• Overview of HT Resource Usage.

• HT and the Data TLB.

• HT and the FSB.

• The IOQ Depth Was Increased.

• Thread Distribution to Logical Processors.

• Load Balancing.

• HT and the Processor Caches.

• Executing Identical Threads.

• Halt Usage.

• Thread Synchronization.

• WCB Usage.

• HT and Serializing Instructions.

• HT and the Microcode Update Feature. ...