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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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Locking a Cache Line

When the processor begins a locked RMW operation, there are several possible cases:

  • the semaphore isn't in the cache.

  • the semaphore is in the cache in the E state.

  • the semaphore is in the cache in the S state.

  • the semaphore is in the cache in the M state.

Intel® documentation states that the Pentium® 4 processor implements cache line locking in areas of memory designated as WB memory. It should be noted that Intel® provides almost no information on how this works, but the author is as certain as can be that the following description is accurate.

The Advantage of Cache Line Locking

FSB locking is inefficient—for the duration of a processor's RMW operation, no other FSB agent can initiate a new transaction. If there are a lot ...

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