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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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Data Bus Parity

Introduction

Table 51-3 on page 1271 defines the data signal lines that each of the four data parity bits are associated with.

Table 51-3. Data Parity Coverage
Data Parity SignalProvides even parity for the overall pattern consisting of:
DP0#
  • Group 0 in 1st qword.

  • Group 1 in 2nd qword.

  • Group 2 in 3rd qword.

  • Group 3 in 4th qword.

DP1#
  • Group 1 in 1st qword.

  • Group 2 in 2nd qword.

  • Group 3 in 3rd qword.

  • Group 0 in 4th qword.

DP2#
  • Group 2 in 1st qword.

  • Group 3 in 2nd qword.

  • Group 0 in 3rd qword.

  • Group 1 in 4th qword.

DP3#
  • Group 3 in 1st qword.

  • Group 0 in 2nd qword.

  • Group 1 in 3rd qword.

  • Group 2 in 4th qword.

As shown in Figure 51-15 on page 1272, the four parity bits for each 32-byte block of data are driven in the BCLK cycle immediately following the BCLK ...

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