Data Bus Parity
Introduction
Table 51-3 on page 1271 defines the data signal lines that each of the four data parity bits are associated with.
Data Parity Signal | Provides even parity for the overall pattern consisting of: |
---|---|
DP0# |
|
DP1# |
|
DP2# |
|
DP3# |
|
As shown in Figure 51-15 on page 1272, the four parity bits for each 32-byte block of data are driven in the BCLK cycle immediately following the BCLK ...
Get The Unabridged Pentium 4 IA32 Processor Genealogy now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.