Caching from SM Memory
Background
It is important to note that to the processor's caches, a memory address is a memory address: the caches do not differentiate between accesses to SM RAM and to regular system memory. This being the case, if the memory address range that is used to access SM RAM (while the processor is in SMM) partially or fully overlaps an address range in system memory that holds OS and/or application information, then one of the following two strategies must be employed:
The overlapping memory address range can be designated as UC memory in the MTTRs. The processor will not cache any information from SM RAM or from regular system memory.
The overlapping memory address range can be designated as cacheable memory (i.e., WP, WT ...
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