The IO APIC
The Purpose of the IO APIC
When a device adapter issues an interrupt request to a processor, it is issued in one of two forms:
By asserting one of the IRQ signal lines.
By performing an MSI write transaction in the form of a memory-mapped IO write [see “Message Signaled Interrupts (MSI)” on page 1584].
The IO APIC is incorporated within the chipset and its inputs are connected to the IRQ lines (and possibly to the SMI# signal line). When a device adapter asserts an IRQ line or when the system board logic asserts the SMI# signal, the IO APIC converts this into an interrupt message and transmits it to the processors either over the 3-wire APIC bus (for the Pentium® and P6 processors families; see Figure 61-28 on page 1568), or the FSB ...
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