MP Systems Need a Better Interrupt Distribution Mechanism
As just described, the legacy interrupt delivery mechanism interrupts the processor by asserting the processor's INTR input signal. The processor recognizes the interrupt on the next instruction boundary and must then perform an Interrupt Acknowledge transaction on its FSB to obtain the interrupt vector from the interrupt controller. This method is inefficient in the following ways:
Refer to Figure 61-3 on page 1502. Using the INTR signal to deliver interrupts to the processors in a multiprocessor (MP) system is a poor approach. All of the interrupts would be delivered to the processor that is connected to the output of the master 8259A PIC and that processor would have the ...