Table 61-1 on page 1518 is a subset of Table 14-4 on page 267 and shows the priority relationship of the various types of interrupts to each other in the event that multiple interrupt types are received by the Local APIC simultaneously. As an example, if the processor were to simultaneously receive an SMI and an NMI interrupt, the SMI would be serviced first followed by the NMI (when the processor has completed servicing the SMI).
|Class||Class Description||Ranking Within Class (highest shown first)||Handled by APIC?|
|3 Highest Priority||Special external hardware interrupts|
Flush. The chipset asserts the FLUSH# signal to the processor to force a cache flush (e.g., on a switch to SMM). ...