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Top-Down Digital VLSI Design by Hubert Kaeslin

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Chapter 6

The Case For Synchronous Design

Abstract

Digital circuits and systems are exposed to timing problems unless all transients are allowed to come to an end before data items are being locked in a memory element, hence the need for rigorously regulating all state changes and data storage operations. Conceptually, one can distinguish between synchronous clocking and self-timed operation. And then there are all sorts of unstructured ad hoc clocking styles. We first introduce and compare these approaches before commenting on why synchronous clocking is still considered the best choice for staying clear of timing problems in the context of digital VLSI. A number of detailed design rules are then derived from two general principles. The ...

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