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[bib04_1] [1] C. Pixley. A Theory and Implementation of Sequential Hardware Equivalence. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 11(12):1469–1478, December 1992.

[bib04_2] [2] J. Burch and V. Singhal. Robust Latch Mapping for Combinational Equivalence Checking. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pages 563–569, November 1998.

[bib04_3] [3] C. van Eijk and J. Jess. Detection of Equivalent State Variables in Finite State Machine Verification. Proceedings of International Workshop on Logic Synthesis, May 1995.

[bib04_4] [4] H. Cho and C. Pixley. Apparatus and Method for Deriving Correspondences between Storage Elements of a First Circuit Model and Storage Elements of ...

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