O'Reilly logo

Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

Chapter 12 The One-Hot State Machine for FPGAs

For Field Programmable Gate Arrays (FPGAs), the normal method of designing state machines is not optimal. This is because FPGAs are made up of logic blocks, unlike Application Specific Integrated Circuits (ASICs), which can be designed using simple logic gates. Each logic block in an FPGA has one or more flip-flops plus some limited combinatorial logic, making for an abundance of flip-flops. For creating large combinatorial logic terms, however, many logic blocks are often involved, which requires connecting these blocks through slow interconnect. If we look at the RTL Verilog code for the simple memory controller state machine in Chapter 10, the resulting gate level implementation will probably ...

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required