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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 15 The Phase Locked Loop (PLL)

The Phase Locked Loop (PLL) is particularly important in communication hardware designs. It is used to create a clock that is of a known frequency, from another clock that is not quite regular, or from a data stream that has the clock embedded in it. The digital PLL described here takes an input that tells it the frequency of the clock that it is supposed to generate. If the frequency is fixed, this can be coded as a constant, further optimizing the code. The PLL looks at an incoming signal to attempt to match its own edges to that of the incoming signal. This is how it locks onto the phase of the incoming clock. If the edges do not line up (i.e., the phases do not match), the PLL must attempt to adjust ...

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