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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 18 The Parity Generator and Checker

Parity generation and parity checking is a simple, but useful form of error detection that is incorporated in many devices. For every n bits on a bus, an extra parity bit is generated and appended to the bus. The two types of parity are even parity and odd parity. If we are using even parity, we count the number of 1’s in the data word of n bits. If there are an odd number of 1s, then the parity bit will be a 1 so that, including the parity bit, the number of 1s are an even number. If there are already an even number of bits, then the parity bit is 0. Similarly for odd parity, we want the total number of 1s, including the parity bit, to be an odd number. Some examples of odd and even parity are shown ...

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