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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 20 The Checksum

A checksum is a simple but effective way of verifying a long sequence of data. All a checksum generator does is add each data word in the sequence on each clock cycle and output the inverted, cumulative sum. All of the carry bits simply overflow the adder and are discarded. This inverted sum is then stored at the end of the sequence of data. When the data is read back, the checksum verifier again adds each data word. When the checksum is passed through the verifier, the resulting output should be zero. If it is not zero, some data has been corrupted and the sequence must be re-read or discarded. Of course there is a small possibility that the data gets corrupted but ends up with the correct checksum. The probability of ...

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