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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 22 The Random Access Memory (RAM)

The Random Access Memory (RAM) is an important part of many designs. Now that complex systems are being designed on a chip, the accompanying system RAM is often moved onto the chip also. This chapter describes the Verilog code for the very simple RAM shown in Figure 22-1. Note that this RAM is asynchronous in that there is no common clock. Writing takes place with respect to the write signal, whereas reading takes place with respect to the output enable signal. This is about as simple an example of asynchronous RAM as you can have. For an example of a synchronous RAM, see the Dual Port RAM described in the next chapter.

Figure 22-1 A simple 16 by 8 RAM.

22.1 Implementation Code

Following is the Verilog ...

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