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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 25 The Synchronizing FIFO

The Synchronizing FIFO is a memory buffer similar to the Synchronous FIFO described in the previous chapter. Unlike a Synchronous FIFO that has a single clock, the Synchronizing FIFO uses two clocks, one for the receiver logic and one for the transmitter logic. These clocks are asynchronous with respect to each other. That means that there is no defined phase relationship between them. The job of the Synchronizing FIFO is to synchronize the two sets of logic without losing or corrupting data. For this reason, this type of FIFO is much more complex to design. Note that this design has status bits (full, empty, half) that are generated using combinatorial logic of signals clocked off both clocks. These signals ...

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