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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 26 The SRAM/ROM Controller

This chapter describes a simple state machine to control a Static Random Access Memory (SRAM) or Read Only Memory (ROM). Obviously, the difference between a ROM controller and an SRAM controller is simply that the ROM data cannot be written, so the write enable input to the chip should be tied high when the controller is used to access a ROM.

The connection between the processor, the SRAM, and the controller would typically look like the diagram in Figure 26-1 where the data and address buses are connected directly to the SRAM. It is the output enable (OE) and write enable (WE) to the SRAM, and the acknowledge (ACK) to the processor that must be derived from the processor address strobe (AS) and read/write ...

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