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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 27 The Synchronous SRAM Controller

A relatively new type of SRAM has been developed in order to interface to a very fast processor. This type of SRAM is called a Synchronous SRAM (SSRAM) because the inputs and outputs are synchronized to a single clock. This makes it especially good for use with a Reduced Instruction Set Computer (RISC) type processor because these processors tend to execute one or more instructions per clock cycle. When burst accesses of the SSRAM are required, the SSRAM can execute a read or write each cycle after an initial one or two cycle delay. This allows the processor to execute instructions at full speed, without the need to wait for a memory access to complete, if the processor allows pipelined accesses. During ...

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