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Verilog Designer’s Library by Cupertino CA Bob Zeidman - Zeidman Consulting

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Chapter 29 The Fast Page Mode DRAM Controller

This chapter describes a controller for a Fast Page Mode Dynamic Random Access Memory. The difference between a fast page DRAM and a normal DRAM is that the fast page DRAM keeps the entire page of data, addressed by the row address, active as long as the Row Address Strobe (RAS) is kept asserted. When a new access is required to that same page, only the CAS address needs to be supplied while toggling the Column Address Strobe (CAS). These page accesses are very fast, as the name implies, with respect to a normal DRAM access. Typically they require about half the normal access time. The concept here is that most processor accesses occur to data that is localized. In other words, if a particular memory ...

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