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Vertical 3D Memory Technologies by Betty Prince

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3Gate-All-Around (GAA) Nanowire for Vertical Memory

3.1 Overview of GAA Nanowire Memories

Vertical gate-all-around (GAA) nanowire (NW) charge-trapping (CT) memories have been developed with both single-crystal silicon channels and with polycrystal silicon channels. Both types of memory and their development are discussed in this chapter. The evolution toward junctionless memory transistors for long GAA NW strings is also covered. Single-crystal nanowire channels can be made from silicon fins or from stacking layers of dielectric alternated with a sacrificial material. Polysilicon NW CT memory stacks have been shown to benefit from radial configuration and also from the small radius of the NW in scaled arrays. Stacked NW horizontal channel CT NAND memory string processes are discussed. Vertical channel NW CT memories both deposited in an etched channel and deposited on the outside of a cylindrical channel using a replacement technology are also covered. This chapter discusses the technology and cell development of these memory devices, and Chapter 4 discusses their product development.

3.2 Single-Crystal Silicon GAA Nanowire CT Memories

3.2.1 Overview of Single-Crystal Silicon GAA CT Memories

The early GAA memories used single-crystal silicon fins formed from the surface of the silicon wafer as the starting point for making a single-crystal silicon wire. This wire was detached from the substrate and oxidized, and then CT and gate materials were added. Initially, vertically ...

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