63D Stacking of RAM–Processor Chips Using TSV

6.1 Overview of 3D Stacking of RAM–Processor Chips with TSV

Three-dimensional (3D) chips stacked and connected with vertical through-silicon-vias (TSV) entered the market in about 2013 led by stacked chips of homogeneous memory and followed in 2014 by early stacked heterogeneous memory and logic chip systems. The 3D configuration can replace shrinking the planar chip, which is nearing its limit for being a cost-effective technology. It can also replace two-dimensional (2D) chips of memory integrated with logic, which have developed some system issues such as noise due to long interconnects. Three-dimensional chip stacking with TSV provides smaller footprints, higher performance, lower power, and higher reliability through less system noise. Early use of configurable passive interposers helped connect standard chips in three dimensions. Standards for chips redesigned for better placement of 3D connections followed. Early standards for chips reconfigured for 3D TSV packaging have been posted, and at least one industry consortium is discussing new standards for 3D stacked chips using TSV.

Design issues include both new computer-aided design (CAD) tools for 3D optimization and methodologies for repartitioning systems in three dimensions. Both systems of homogenous die, such as memory systems and field-programmable gate arrays (FPGA), and systems of heterogeneous die can benefit from vertical 3D TSV integration. Early examples of heterogeneous ...

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