VHDL-2008

VHDL-2008

by Peter J. Ashenden, Jim Lewis
Released November 2007
Publisher(s): Morgan Kaufmann
ISBN: 9780080557571

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Book description

VHDL-2008: Just the New Stuff, as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed.

* First in the market describing the new features of VHDL 2008;* Just the new features, so existing users and implementers can focus on what's new; * Helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books. * Authoritative, written by experts in the area; * Tutorial style, making it more accessible than the VHDL Standard Language Reference Manual.

Table of contents

  1. Copyright
  2. The Morgan Kaufmann Series in Systems on Silicon
  3. Preface
    1. Acknowledgments
  4. 1. Enhanced Generics
    1. 1.1. Generic Types
    2. 1.2. Generic Lists in Packages
    3. 1.3. Local Packages
    4. 1.4. Generic Lists in Subprograms
    5. 1.5. Generic Subprograms
      1. 1.5.1. Uninstantiated Methods in Protected Types
    6. 1.6. Generic Packages
    7. 1.7. Use Case: Generic Memories
  5. 2. Other Major Features
    1. 2.1. External Names
    2. 2.2. Force and Release
    3. 2.3. Context Declarations
    4. 2.4. Integrated PSL
    5. 2.5. IP Encryption
      1. 2.5.1. Key Exchange
    6. 2.6. VHDL Procedural Interface (VHPI)
      1. 2.6.1. Direct Binding
      2. 2.6.2. Tabular Registration and Indirect Binding
      3. 2.6.3. Registration of Applications and Libraries
  6. 3. Type System Changes
    1. 3.1. Unconstrained Element Types
      1. 3.1.1. Composite Types
      2. 3.1.2. Subtype Indications and Constraints
      3. 3.1.3. Use of Composite Subtypes
        1. Variable and Signal Declarations
        2. Constant Declarations
          1. Attribute Specifications
          2. Allocated Objects
        3. Interface Objects
      4. Summary: Determining Array Index Ranges
      5. Type Conversions
        1. Alias Declarations and Subtype Attributes
      6. Resolved Composite Subtypes
    2. 3.2. Resolved Elements
  7. 4. New and Changed Operations
    1. 4.1. Array/Scalar Logical Operations
    2. 4.2. Array/Scalar Addition Operators
    3. 4.3. Logical Reduction Operators
    4. 4.4. Condition Operator
    5. 4.5. Matching Relational Operators
    6. 4.6. Maximum and Minimum
    7. 4.7. Mod and Rem for Physical Types
    8. 4.8. Shift Operations
    9. 4.9. Strength Reduction and ‘X’ Detection
  8. 5. New and Changed Statements
    1. 5.1. Conditional and Selected Assignments
      1. 5.1.1. Sequential Signal Assignments
      2. 5.1.2. Forcing Assignments
      3. 5.1.3. Variable Assignments
    2. 5.2. Matching Case Statements
      1. 5.2.1. Matching Selected Assignments
    3. 5.3. If and Case Generate
      1. 5.3.1. Configuration of If and Case Generate
  9. 6. Modeling Enhancements
    1. 6.1. Signal Expressions in Port Maps
    2. 6.2. All Signals in Sensitivity List
    3. 6.3. Reading Out-Mode Ports and Parameters
    4. 6.4. Slices in Aggregates
    5. 6.5. Bit-String Literals
  10. 7. Improved I/O
    1. 7.1. The To_string Functions
      1. 7.1.1. Predefined To_string Functions
      2. 7.1.2. Overloaded To_string Functions
      3. 7.1.3. The to_ostring and To_hstring Functions
    2. 7.2. The Justify Function
    3. 7.3. Newline Formatting
    4. 7.4. Read and Write Operations
    5. 7.5. The Tee Procedure
    6. 7.6. The Flush Procedure
  11. 8. Standard Packages
    1. 8.1. The Std_logic_1164 Package
    2. 8.2. The Numeric_bit and Numeric_std Packages
    3. 8.3. The Numeric Unsigned Packages
    4. 8.4. The Fixed-Point Math Packages
    5. 8.5. The Floating-Point Math Packages
    6. 8.6. The Standard Package
    7. 8.7. The Env Package
    8. 8.8. Operator Overloading Summary
    9. 8.9. Conversion Function Summary
    10. 8.10. Strength Reduction Function Summary
  12. 9. Miscellaneous Changes
    1. 9.1. Referencing Generics in Generic Lists
    2. 9.2. Function Return Subtype
    3. 9.3. Qualified Expression Subtype
    4. 9.4. Type Conversions
    5. 9.5. Case Expression Subtype
    6. 9.6. Subtypes for Port and Parameter Actuals
    7. 9.7. Static Composite Expressions
    8. 9.8. Static Ranges
    9. 9.9. Use Clauses, Types, and Operations
    10. 9.10. Hiding of Implicit Operations
    11. 9.11. Multidimensional Array Alias
    12. 9.12. Others in Aggregates
    13. 9.13. Attribute Specifications in Package Bodies
    14. 9.14. Attribute Specification for Overloaded Subprograms
    15. 9.15. Integer Expressions in Range Bounds
    16. 9.16. Action on Assertion Violations
    17. 9.17. ’Path-Name and ’Instance_Name
    18. 9.18. Non-Nesting of Architecture Region
    19. 9.19. Purity of Now
    20. 9.20. Delimited Comments
    21. 9.21. Tool Directives
    22. 9.22. New Reserved Words
    23. 9.23. Replacement Characters
  13. 10. What’s Next
    1. 10.1. Object-Oriented Class Types
      1. 10.1.1. Standard Components Library
    2. 10.2. Randomization
    3. 10.3. Functional Coverage
    4. 10.4. Alternatives
    5. 10.5. Getting Involved

Product information

  • Title: VHDL-2008
  • Author(s): Peter J. Ashenden, Jim Lewis
  • Release date: November 2007
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780080557571