VLSI and Hardware Implementations using Modern Machine Learning Methods

VLSI and Hardware Implementations using Modern Machine Learning Methods

by Sandeep Saini, Kusum Lata, G.R. Sinha
Released December 2021
Publisher(s): CRC Press
ISBN: 9781000523843

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Book description

This book aims to provide the latest machine learning based methods, algorithms, architectures, and frameworks designed for VLSI design with focus on digital, analog and mixed-signal design techniques, device modeling, physical design, hardware implementation, testability, reconfigurable design, synthesis and verification, and related areas.

Table of contents

  1. Cover
  2. Half Title
  3. Title Page
  4. Copyright Page
  5. Contents
  6. Preface
  7. About the Editors
  8. Contributors
  9. Chapter 1 VLSI and Hardware Implementation Using Machine Learning Methods: A Systematic Literature Review
    1. 1.1 Introduction
    2. 1.2 Motivation
    3. 1.3 Contributions
    4. 1.4 Literature Review
    5. 1.5 Methods
      1. 1.5.1 Search Strategy
      2. 1.5.2 Inclusion and Exclusion Rules
      3. 1.5.3 Data Extraction Strategy
      4. 1.5.4 Synthesis of Extracted Data
      5. 1.5.5 Results and Discussions
      6. 1.5.6 Study Overview
    6. 1.6 Hardware Implementation of ML/AI Algorithms
      1. 1.6.1 FPGA-Based Implementation
      2. 1.6.2 GPU-Based Implementation
      3. 1.6.3 ASICs-Based Implementations
      4. 1.6.4 Other Implementations
      5. 1.6.5 SLR Discussions and Recommendations
    7. 1.7 Conclusions
    8. References
  10. Chapter 2 Machine Learning for Testing of VLSI Circuit
    1. 2.1 Introduction
    2. 2.2 Machine Learning Overview
    3. 2.3 Machine Learning Applications in IC Testing
    4. 2.4 ML in Digital Testing
    5. 2.5 ML in Analog Circuit Testing
    6. 2.6 ML in Mask Synthesis and Physical Placement
    7. 2.7 Conclusion
    8. Acknowledgment
    9. References
  11. Chapter 3 Online Checkers to Detect Hardware Trojans in AES Hardware Accelerators
    1. 3.1 Introduction: Background and Driving Forces
      1. 3.1.1 Threat Model
    2. 3.2 Proposed Methodology: Online Monitoring for HT Detection
      1. 3.2.1 Reliability-Based Node Selection to Insert Checker
    3. 3.3 Results and Discussion
      1. 3.3.1 Results of Benchmark Circuits
      2. 3.3.2 Results for AES Encryption Unit
    4. 3.4 Conclusion
    5. References
  12. Chapter 4 Machine Learning Methods for Hardware Security
    1. 4.1 Introduction
    2. 4.2 Preliminaries
      1. 4.2.1 Machine Learning Models Used in Hardware Security
        1. 4.2.1.1 Supervised Learning
          1. 4.2.1.1.1 Support Vector Machines
          2. 4.2.1.1.2 One-Class Classifiers
          3. 4.2.1.1.3 Bayesian Classifiers
          4. 4.2.1.1.4 Linear Regression
          5. 4.2.1.1.5 Multivariate Adaptive Regression Splines (MARS)
          6. 4.2.1.1.6 Decision Tree (DT)
          7. 4.2.1.1.7 Random Forest (RF)
          8. 4.2.1.1.8 Logistic Regression (LR)
          9. 4.2.1.1.9 AdaBoost or Adaptive Boosting
          10. 4.2.1.1.10 Artificial Neural Networks
          11. 4.2.1.1.11 Convolutional Neural Network
          12. 4.2.1.1.12 AutoEncoder
          13. 4.2.1.1.13 Recurrent Neural Network
          14. 4.2.1.1.14 Extreme Learning Machine
          15. 4.2.1.1.15 Long Short-Term Memory
          16. 4.2.1.1.16 Half-Space Trees
          17. 4.2.1.1.17 K-Nearest Neighbors (KNN)
      2. 4.2.2 Unsupervised Learning
        1. 4.2.2.1 Clustering Algorithms
        2. 4.2.2.2 K-means Clustering Algorithm
        3. 4.2.2.3 Partitioning Around Medoids (PAM)
        4. 4.2.2.4 Density-Based Spatial Clustering (DBSCAN) and Ordering Points to Identify the Clustering Structure (OPTICS)
      3. 4.2.3 Feature Selection and Dimensionality Reduction
        1. 4.2.3.1 Genetic Algorithms
        2. 4.2.3.2 Pearson's Correlation Coefficient
        3. 4.2.3.3 Minimum Redundancy Maximum Relevance (mRMR)
        4. 4.2.3.4 Principal Component Analysis
        5. 4.2.3.5 Two-Dimensional Principal Component Analysis
        6. 4.2.3.6 Self-Organizing Maps (SOMs)
    3. 4.3 Hardware Security Challenges Addressed by Machine Learning
      1. 4.3.1 Hardware Trojans
      2. 4.3.2 Reverse Engineering
      3. 4.3.3 Side-Channel Analysis
      4. 4.3.4 IC Counterfeiting
      5. 4.3.5 IC Overproduction
    4. 4.4 Present Protection Mechanisms in Hardware Security
      1. 4.4.1 Hardware Trojan Detection
      2. 4.4.2 IC Counterfeiting Countermeasures
      3. 4.4.3 Reverse Engineering Approach
    5. 4.5 Machine-Learning–Based Attacks and Threats
      1. 4.5.1 Side-Channel Analysis
        1. 4.5.1.1 Side-Channel Analysis for Cryptographic Key Extraction
        2. 4.5.1.2 Side-Channel Analysis for Instruction-Level Disassembly
      2. 4.5.2 IC Overbuilding
    6. 4.6 Emerging Challenges and New Directions
    7. References
  13. Chapter 5 Application-Driven Fault Identification in NoC Designs
    1. 5.1 Introduction
    2. 5.2 Related Work
    3. 5.3 Identification of Vulnerable Routers
      1. 5.3.1 Proposed Mathematical Model for Router Reliability
      2. 5.3.2 Determination of the Vulnerable Routers Using Simulation
      3. 5.3.3 Look-up-Table (LuT) Generation from Experimental Data
    4. 5.4 The Proposed Methodology for the Identification of Vulnerable Routers
      1. 5.4.1 Classification of Application Traffic Using Machine Learning
        1. 5.4.1.1 Dataset Generation
        2. 5.4.1.2 Feature Vector Extraction
        3. 5.4.1.3 Training of the ML Model
        4. 5.4.1.4 Working of the Trained Model
      2. 5.4.2 Validation of the ML Model for Traffic Classification
      3. 5.4.3 Identification of Vulnerable Routers Using Look-up-Table (LuT)
    5. 5.5 Future Work and Scope
      1. 5.5.1 Pooling of Unused Routers: A Structural Redundancy Approach
    6. 5.6 Conclusion
    7. References
  14. Chapter 6 Online Test Derived from Binary Neural Network for Critical Autonomous Automotive Hardware
    1. 6.1 Autonomous Vehicles
      1. 6.1.1 Levels of Autonomy
      2. 6.1.2 Safety Concerns
    2. 6.2 Traditional VLSI Testing
    3. 6.3 Functional Safety
      1. 6.3.1 Fault Detection Time Interval
    4. 6.4 Discussion 1: Binary Convolutional Neural Network
      1. 6.4.1 One Layer of the Convolutional Network
      2. 6.4.2 Forward Propagation
      3. 6.4.3 Binary Neural Autoencoder Model with Convolutional 1D
      4. 6.4.4 Binary Neural Network Model with Convolutional 2D
      5. 6.4.5 Backward Propagation
    5. 6.5 Discussion 2: On-Chip Compaction
      1. 6.5.1 Binary Recurrent Neural Networks
      2. 6.5.2 Forward Propagation
      3. 6.5.3 Backpropagation
      4. 6.5.4 Advantages and Limitations
    6. 6.6 Discussion 3: Binary Deep Neural Network for Controller Variance Detection
    7. 6.7 Conclusion
    8. Acknowledgment
    9. References
  15. Chapter 7 Applications of Machine Learning in VLSI Design
    1. 7.1 Introduction
    2. 7.2 Machine Learning Preliminaries
    3. 7.3 System-Level Design
    4. 7.4 Logic Synthesis and Physical Design
    5. 7.5 Verification
    6. 7.6 Test, Diagnosis, and Validation
    7. 7.7 Challenges
    8. 7.8 Conclusions
    9. References
  16. Chapter 8 An Overview of High-Performance Computing Techniques Applied to Image Processing
    1. 8.1 Introduction
      1. 8.1.1 Context
      2. 8.1.2 Concepts
    2. 8.2 HPC Techniques Applied to Image Treatment
      1. 8.2.1 Cloud-Based Distributed Computing
      2. 8.2.2 GPU-Accelerated Parallelization
      3. 8.2.3 Parallelization Using GPU Cluster
      4. 8.2.4 Multicore Architecture
    3. 8.3 Neural Networks
      1. 8.3.1 Convolutional Neural Network (CNN)
      2. 8.3.2 Generative Adversarial Network (GAN)
      3. 8.3.3 HPC Techniques Applied to Neural Networks
    4. 8.4 Machine Learning Applications Hardware Design
      1. 8.4.1 FPGA
      2. 8.4.2 SVM
    5. 8.5 Conclusions
    6. Notes
    7. References
  17. Chapter 9 Machine Learning Algorithms for Semiconductor Device Modeling
    1. 9.1 Introduction
    2. 9.2 Semiconductor Device Modeling
    3. 9.3 Related Work
    4. 9.4 Challenges
    5. 9.5 Machine Learning Fundamentals
      1. 9.5.1 Supervised Machine Learning Algorithms
      2. 9.5.2 Unsupervised Machine Learning Algorithms
      3. 9.5.3 Deep Learning Algorithms
    6. 9.6 Case Study: Thermal Modeling of the GaN HEMT Device
      1. 9.6.1 Experimental Setup
      2. 9.6.2 Results
    7. 9.7 Conclusion
    8. Acknowledgments
    9. References
  18. Chapter 10 Securing IoT-Based Microservices Using Artificial Intelligence
    1. 10.1 Introduction: Background and Driving Forces
    2. 10.2 Previous Work
    3. 10.3 Proposed Work
    4. 10.4 Results
      1. 10.4.1 Components
      2. 10.4.2 Deployment and Testing
    5. 10.5 Result and Discussion
    6. 10.6 Conclusions
    7. References
  19. Chapter 11 Applications of the Approximate Computing on ML Architecture
    1. 11.1 Approximate Computing
      1. 11.1.1 Introduction
      2. 11.1.2 Approximation
      3. 11.1.3 Strategies of Approximation Computing
      4. 11.1.4 What to Approximate
      5. 11.1.5 Error Analysis in Approximate Computing
    2. 11.2 Machine Learning
      1. 11.2.1 Introduction
      2. 11.2.2 Neural Networks
        1. 11.2.2.1 Architecture
        2. 11.2.2.2 Abilities and Disabilities
      3. 11.2.3 Machine Learning vs. Neural Network
      4. 11.2.4 Classifications of Neural Networks in Machine Learning
        1. 11.2.4.1 Artificial Neural Network (ANN)
          1. 11.2.4.1.1 Feedforward ANN
          2. 11.2.4.1.2 Abilities of Artificial Neural Network (ANN)
        2. 11.2.4.2 Convolution Neural Network (CNN)
      5. 11.2.5 Novel Algorithm in ANN
        1. 11.2.5.1 Introduction
        2. 11.2.5.2 Weights of Neurons
        3. 11.2.5.3 Weight vs. Bias
        4. 11.2.5.4 Neuron (Node)
          1. 11.2.5.4.1 Bias (Offset)
          2. 11.2.5.4.1 Bias (Offset)
    3. 11.3 Approximate Machine Learning Algorithms
      1. 11.3.1 Introduction
      2. 11.3.2 Approximate Computing Techniques
      3. 11.3.3 Approximate Algorithms for Machine Learning
      4. 11.3.4 Results and Analysis
    4. 11.4 Case Study 1: Energy-Efficient ANN Using Alphabet Set Multiplier
      1. 11.4.1 Introduction
      2. 11.4.2 8-bit 4 Alphabet ASM
      3. 11.4.3 Four Alphabet ASMs Using CSHM Architecture
        1. 11.4.3.1 Rounding Logic
      4. 11.4.4 Multiplier-Less Neuron
      5. 11.4.5 Results and Analysis
    5. 11.5 Case Study 2: Efficient ANN Using Approximate Multiply-Accumulate Blocks
      1. 11.5.1 Introduction
      2. 11.5.2 SMAC Neuron's Architecture
      3. 11.5.3 The Architecture of SMAC ANN
      4. 11.5.4 Approximate Adder
      5. 11.5.5 Approximate Multiplier
      6. 11.5.6 Results and Analysis
    6. 11.6 Conclusion
    7. References
  20. Chapter 12 Hardware Realization of Reinforcement Learning Algorithms for Edge Devices
    1. 12.1 Introduction
      1. 12.1.1 Reinforcement Learning and Markov Decision Process
      2. 12.1.2 Hardware for Reinforcement Learning at the Edge
    2. 12.2 Background
    3. 12.3 Hardware Realization of Simple Reinforcement Learning Algorithm
      1. 12.3.1 Architecture-Level Description
      2. 12.3.2 Flow of Data in the Hardware Architecture
    4. 12.4 Results and Analysis of SRL Hardware Architecture
    5. 12.5 Q-Learning and SRL Algorithm Applications
    6. 12.6 Future Work: Application and Hardware Design Overview
      1. 12.6.1 Hardware Design Overview
    7. 12.7 Conclusion
    8. Acknowledgment
    9. References
  21. Chapter 13 Deep Learning Techniques for Side-Channel Analysis
    1. 13.1 Introduction
    2. 13.2 Preliminaries
      1. 13.2.1 Framework for Implementation Vulnerability Analysis
    3. 13.3 Profiled Side-Channel Attacks
      1. 13.3.1 Deep Learning Architecture for Analysis
      2. 13.3.2 Convolutional Neural Networks
    4. 13.4 Protected Countermeasure Techniques
      1. 13.4.1 Unrolled Implementation
      2. 13.4.2 Threshold Implementation
    5. 13.5 Case Study of GIFT Cipher
      1. 13.5.1 GIFT Algorithm Description
      2. 13.5.2 Implementation Profiles
      3. 13.5.3 Round (Naive) Implementation
      4. 13.5.4 (Un)Rolled Implementation
      5. 13.5.5 Partially (Un)Rolled Implementation with Threshold Implementation Countermeasure
      6. 13.5.6 Experiment Setup
    6. 13.6 Description of PSCA on GIFT Using DeepSCA
      1. 13.6.1 Vulnerability Analysis
    7. 13.7 Conclusion and Future Work
    8. Acknowledgments
    9. References
  22. Chapter 14 Machine Learning in Hardware Security of IoT Nodes
    1. 14.1 Introduction
    2. 14.2 Classification of Hardware Attacks
      1. 14.2.1 Hardware Trojan Taxonomy
        1. 14.2.1.1 Insertion Phase
        2. 14.2.1.2 Level of Description
        3. 14.2.1.3 Activation Mechanism
        4. 14.2.1.4 Effects of Hardware Trojans
        5. 14.2.1.5 Location
      2. 14.2.2 Types of Hardware Trojans
    3. 14.3 Countermeasures for Threats of Hardware Trojans in IoT Nodes
      1. 14.3.1 Hardware Trojan Detection Approaches
      2. 14.3.2 Hardware Trojan Diagnosis
      3. 14.3.3 Hardware Trojan Prevention
    4. 14.4 Machine Learning Models
      1. 14.4.1 Supervised Machine Learning
      2. 14.4.2 Unsupervised Machine Learning
      3. 14.4.3 Dimensionality Reduction & Feature Selection
      4. 14.4.4 Design Optimization
    5. 14.5 Proposed Methodology
      1. 14.5.1 Stage 1: Analysis of IoT Circuit Structure Features
      2. 14.5.2 Stage 2: Feature Extraction from Netlist
      3. 14.5.3 Stage 3: Hardware Trojan Classifier Training
      4. 14.5.4 Stage 4: Detection of Hardware Trojan
      5. 14.5.5 Comparison of HT Detection Models Based on ML
    6. 14.6 Conclusion
    7. References
  23. Chapter 15 Integrated Photonics for Artificial Intelligence Applications
    1. 15.1 Introduction to Photonic Neuromorphic Computing
    2. 15.2 Classification of Photonic Neural Network
    3. 15.3 Photonic Neuron and Synapse
    4. 15.4 Conclusion
    5. References
  24. Index

Product information

  • Title: VLSI and Hardware Implementations using Modern Machine Learning Methods
  • Author(s): Sandeep Saini, Kusum Lata, G.R. Sinha
  • Release date: December 2021
  • Publisher(s): CRC Press
  • ISBN: 9781000523843