Skip to Main Content
VLSI Design Methodology Development, First Edition
book

VLSI Design Methodology Development, First Edition

by Thomas Dillinger
June 2019
Intermediate to advanced content levelIntermediate to advanced
752 pages
22h 19m
English
Pearson
Content preview from VLSI Design Methodology Development, First Edition

Chapter 2. VLSI Design Methodology

2.1 IP Design Methodology

The design of an IP core entails the development and release of a set of models for subsequent SoC methodology flow integration. These models are described in the following sections.

2.1.1 A Functional Model for Logic Validation

The functional IP model is compiled into the SoC simulation environment. The model source is commonly provided as part of the IP license, typically in a hardware description language (HDL) format. For hard IP, for added security of the intellectual property, a compiled binary is licensed, with a set of EDA simulation tool application program interface functions to initialize, exercise, and query the behavior. An HDL model can be developed at different levels ...

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.
Start your free trial

You might also like

Modern VLSI Design: System-on-Chip Design, Third Edition

Modern VLSI Design: System-on-Chip Design, Third Edition

Wayne Wolf
Digital Logic Design, 4th Edition

Digital Logic Design, 4th Edition

Brian Holdsworth, Clive Woods

Publisher Resources

ISBN: 9780135657645