VLSI Design Methodology Development, First Edition

Chapter 4. Cell and IP Modeling

4.1 Functional Modeling for Cells and IP

Functional models are written in a specific hardware description language (HDL), for which EDA vendors have developed corresponding simulation tools. The semantics of an HDL model consist of a set of concurrent sequential processes (CSPs). In short, a set of model processes (or procedures) are compiled. Each process has an input sensitivity list of signals; a transition on a signal in that list results in the execution of the statements in the process. Evaluation of the statements in the process/procedure proceeds sequentially to completion (or until a wait statement clause is encountered). All model processes are pending concurrently, and once active, they may execute ...