VLSI Design Methodology Development, First Edition

Chapter 8. Placement

8.1 Global Floorplanning of Hierarchical Units

Prior to detailed placement of cells in block netlists (and the global cells at the top of the SoC hierarchy), a physical floorplan of the chip design is required. As briefly described in Section 3.1, the floorplan typically represents the first level of the SoC model hierarchy; it is uncommon to further develop a “floorplan within a floorplan” for the physical design of subsequent levels of the SoC hierarchy. The glue logic functionality at the top hierarchical level is commonly allocated to channels between block floorplan boundaries. An alternative methodology would be to define abutting block floorplan regions and insert global glue logic within various blocks. The advantage ...