VLSI Design Methodology Development, First Edition

Chapter 9. Routing

9.1 Routing Introduction

In early VLSI fabrication processes, the majority of each logic stage delay was associated with the internal circuits. The output loading model used in the cell delay calculation was a summation of the capacitances of the interconnect wires and the input pins of the fan-out cells. Routing tools used this lumped cell load model for timing-driven optimization decisions. As the scaling of VLSI processes progressed, the interconnect wire resistance (per unit length) increased, necessitating a change in the delay model. Replacing the simple stage delay model for a cell to all fan-outs, a more detailed cell plus interconnect R*C delay was introduced, resulting in a unique delay value to individual fan-outs ...