VLSI Design Methodology Development, First Edition

Chapter 17. ECOs

17.1 Application of an Engineering Change

An engineering change order (ECO), as introduced in Section 1.1, reflects a netlist-level modification to an existing design. It is applied at a point in the SoC project schedule after the HDL model, the logically equivalent netlist, and the physical implementation have exited the first “design freeze” milestone, in preparation for the initial SoC tapeout. It may also be applied between tapeouts to represent the design changes identified during prototype silicon bring-up. The key methodology impact to the integration of an ECO is that the changes are not a result of the “top-down” RTL-to-netlist-to-physical design flows used during the main project design phase. The ECO design changes ...