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VLSI Design Methodology Development, First Edition
book

VLSI Design Methodology Development, First Edition

by Thomas Dillinger
June 2019
Intermediate to advanced content levelIntermediate to advanced
752 pages
22h 19m
English
Pearson
Content preview from VLSI Design Methodology Development, First Edition

Chapter 18. Physical Design Verification

18.1 Design Rule Checking (DRC)

As introduced in Section 2.2, the DRC tool applies a set of layout operations and measures to the physical design data and reports any rule violations. The sequence of operations and measures, called the runset, is released by the foundry as part of the PDK. Currently, there is no (de facto) industry standard for the runset command syntax (e.g., operations such as INTERSECT and EXPAND/SHRINK and measure checks such as SPACE, OVERLAP, and AREA). An SoC project manager needs to review which EDA vendor DRC tools are supported by the foundry and coordinate with the CAD team for installation and flow support of the PDK runset corresponding to the EDA software licenses available. ...

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Publisher Resources

ISBN: 9780135657645